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BU-65170/61580 and BU-61585
MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT, ADVANCED COMMUNICATION ENGINE (ACE)
ACE User's Guide Also Available
DESCRIPTION
DDC's BU-65170, BU-61580 and BU-61585 Bus Controller / Remote Terminal / Monitor Terminal (BC/RT/MT) Advanced Communication Engine (ACE) terminals comprise a complete integrated interface between a host processor and a MIL-STD-1553 A and B or STANAG 3838 bus. The ACE series is packaged in a 1.9 square-inch, 70-pin, low-profile, cofired MultiChip Module (MCM) ceramic package that is well suited for applications with stringent height requirements. The BU-61585 ACE integrates dual transceiver, protocol, memory management, processor interface logic, and a total of 12K words of RAM in a choice of DIP or flat pack packages. The BU-61585 requires +5 V power and either -15 V or -12 V power. The BU-61585 internal RAM can be configured as 12K x 16 or 8K x 17. The 8K x 17 RAM feature provides capability for memory integrity checking by implementing RAM parity generation and verification on all accesses. To minimize board space and "glue" logic, the ACE provides ultimate flexibility in interfacing to a host processor and internal/external RAM. The advanced functional architecture of the ACE terminals provides software compatibility to DDC's Advanced Integrated Multiplexer (AIM) series hybrids, while incorporating a multiplicity of architectural enhancements. It allows flexible operation while off-loading the host processor, ensuring data sample consistency, and supports bulk data transfers. The ACE hybrids may be operated at either 12 or 16 MHz. Wire bond options allow for programmable RT address (hardwired is standard) and external transmitter inhibit inputs.
FEATURES
* Fully Integrated MIL-STD-1553
Interface Terminal Interface
* Flexible Processor/Memory * Standard 4K x 16 RAM and * Optional RAM Parity
Optional 12K x 16 or 8K x 17 RAM Available Generation/Checking
* Automatic BC Retries * Programmable BC Gap Times * BC Frame Auto-Repeat * Flexible RT Data Buffering * Programmable Illegalization * Selective Message Monitor * Simultaneous RT/Monitor Mode
TX/RX_A SHARED RAM CH. A TRANSCEIVER A DATA BUFFERS PROCESSOR DATA BUS
*
TX/RX_A
DATA BUS DUAL ENCODER/DECODER, MULTIPROTOCOL AND MEMORY MANAGEMENT
D15-D0
TX/RX_B
ADDRESS BUS
ADDRESS BUFFERS
A15-A0
PROCESSOR ADDRESS BUS
CH. B
TRANSCEIVER B
TX/RX_B PROCESSOR AND MEMORY INTERFACE LOGIC
TRANSPARENT/BUFFERED, STRBD, SELECT, RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN, MSB/LSB/DTGRT IOEN, MEMENA-OUT, READYD ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR, 8/16-BIT/DTREQ, POLARITY_SEL/DTACK INT PROCESSOR AND MEMORY CONTROL INTERRUPT REQUEST
RT ADDRESS
RTAD4-RTAD0, RTADP
INCMD MISCELLANEOUS CLK_IN, TAG_CLK, MSTCLR,SSFLAG/EXT_TRG
* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY
FIGURE 1. ACE BLOCK DIAGRAM (c) 1992, 1999 Data Device Corporation
TABLE 1. "ACE" SERIES SPECIFICATIONS PARAMETER ABSOLUTE MAXIMUM RATING Supply Voltage ! Logic +5V ! Transceiver +5V ! -15V ! -12V Logic ! Voltage Input Range RECEIVER Differential Input Resistance ! (BU-65170/61580/61585X1, BU-65170/61580/61585X2) (Notes 1-7) ! (BU-65170/61580/61585X3, BU-65170/61580/61585X6) (Notes 1-7) Differential Input Capacitance ! (BU-65170/61580/61585X1, BU-65170/61580/61585X2) (Notes 1-7) ! (BU-65170/61580/61585X3, BU-65170/61580/61585X6) (Notes 1-7) Threshold Voltage, Transformer Coupled, Measured on Stub Common Mode Voltage (Note 7) TRANSMITTER Differential Output Voltage ! Direct Coupled Across 35 , Measured on Bus ! Transformer Coupled Across 70 , Measured on Bus *(BU-65170/61580/61585X1) *(BU-65170/61580/61585X2,X3, X6) Output Noise, Differential (Direct Coupled) Output Offset Voltage, Transformer Coupled Across 70 ohms Rise/Fall Time LOGIC VIH VIL IIH (Vcc=5.5V, VIN=Vcc) IIH (Vcc=5.5V, VIN=2.7V) ! SSFLAG/EXT_TRIG ! All Other Inputs IIL (Vcc=5.5V, VIN=0.4V) ! SSFLAG/EXT_TRIG ! All Other Inputs VOH (Vcc=4.5V, VIH=2.7V, VIL=0.2V, IOH=max) VOL (Vcc=4.5V, VIH=2.7V, VIL=0.2V, IOL=max) IOL ! DB15-DB0, A15-A0, MEMOE/ ADDR_LAT, MEMWR/ ZEROWAIT, DTREQ/16/8, DTACK/POLARITY_SEL MIN TYP MAX UNITS
TABLE 1. "ACE" SERIES SPECIFICATIONS (CONTD) PARAMETER LOGIC (cont'd) ! INCMD, INT MEMENA_OUT, READYD, IOEN, TXA, TXA, TXB, TXB, TX_INH_OUT_A, TX_INH_OUT_B, IOH ! DB15-DB0, A15-A0, MEMOE/ ADDR_LAT, MEMWR/ ZEROWAIT, DTREQ/16/8, DTACK/POLARITY_SEL ! INCMD, INT, MEMENA_OUT, READYD, IOEN, TXA, TXA, TXB, TXB, TX_INH_OUT_A, TX_INH_OUT_B, CI (Input Capacitance) CIO (Bi-directional signal input capacitance) POWER SUPPLY REQUIREMENTS Voltages/Tolerances ! BU-65170/61580/61585X1 * +5V (Logic) * +5V (Ch. A, Ch. B) * -15V (Ch. A, Ch. B) ! BU-65170/61580/61585X2 * +5V (Logic) * +5V (Ch. A, Ch. B) * -12V (Ch. A, Ch. B) ! BU-65170/61580/61585X3, BU-65170/61580/61585X6 * +5V (Logic) * +5V (Ch. A, Ch. B) Current Drain (Total Hybrid) ! BU-65170/61580X1 * +5V (Logic, Ch. A, Ch. B) * -15V (Ch. A, Ch. B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-65170/61580X2 * +5V (Logic, Ch. A, Ch. B) * -12V (Ch. A, Ch. B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-65170/61580X3, BU-65170/61580X6 * +5V (Logic, Ch. A, Ch. B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-61585X1 * +5V (Logic, Ch. A, Ch. B) * -15V (Ch. A, Ch. B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle MIN 3.2 TYP MAX UNITS mA
-0.3 -0.3 -18.0 -18.0 -0.3
7.0 7.0 0.3 0.3 Vcc+0.3
V V V V V
-6.4
mA
11
k
-3.2
mA
2.5
k
50 50
pF pF
10
pF
5
pF
4.5 5.0 5.5 4.5 5.0 5.5 -15.75 -15.0 -14.25 4.5 4.5 -12.6 5.0 5.0 -12.0 5.5 5.5 -11.4
V V V V V V
0.200
0.860 10
Vp-p Vpeak
6
7
9
Vp-p
4.5 4.75
5.0 5.0
5.5 5.25
mA mA
20 18
27 27 10 250 150 300
-250 100 2.0 -10 -692 -346 -794 -397 2.4
Vp-p Vp-p mVp-p, diff mV nsec V V A A A A A V V
95 30 68 105 180 95 30 80 130 230
190 60 108 160 255 190 60 120 185 305
mA mA mA mA mA mA mA mA mA mA
0.8 10 -84 -42 -100 -50
0.4
95 245 360 590 105 30 68 105 180
200 350 500 800 240 60 108 160 255
mA mA mA mA mA mA mA mA mA
6.4
mA
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BU-65170/61580/61585 H1 web-09/02-0
TABLE 1. "ACE" SERIES SPECIFICATIONS (CONTD) PARAMETER
! BU-61585X2
TABLE 1. "ACE" SERIES SPECIFICATIONS (CONTD) PARAMETER
! BU-61585X1
MIN
TYP 105 30 80 130 230
MAX UNITS 240 60 120 185 305 mA mA mA mA mA
MIN
TYP 0.335 0.600 0.860 1.385 0.290 0.590 0.890 1.490
MAX UNITS 0.68 1.06 1.45 2.23 0.59 0.92 1.36 2.16 W W W W W W W W
* +5V (Logic, Ch. A, Ch. B) * -12V (Ch. A, Ch. B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-61585X3, BU-61585X6 * +5V (Logic, Ch. A, Ch. B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle POWER DISSIPATION Total Hybrid ! BU-65170/61580X1 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-65170/61580X2 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-65170/61580X3, BU-65170/61580X6 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-61585X1 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-61585X2 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-61585X3, BU-61585X6 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle Hottest Die ! BU-65170/61580X1 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-65170/61580X2 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-65170/61580X3, BU-65170/61580X6 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle
105 255 370 600
250 400 550 850
mA mA mA mA
* Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-61585X2 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-61585X3, BU-61585X6 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle CLOCK INPUT Frequency ! Nominal Value (programmable) * Default Mode * Software Programmable Option ! Long Term Tolerance * 1553A Mode * 1553B Mode ! Short Term Tolerance, 1 second * 1553A Mode * 1553B Mode ! Duty Cycle * 16 MHz * 12 MHz 1553 MESSAGE TIMING Completion of CPU Write (BC Start)to-Start of Next Message BC Intermessage Gap (Note 8) BC/RT/MT Response Timeout (Note 9) ! 18.5 nominal ! 22.5 nominal ! 50.5 nominal ! 128.0 nominal RT Response Timeout (Note 11) Transmitter Watchdog Timeout THERMAL Thermal Resistance, Junction-to-Case, Hottest Die (JC) ! BU-65170/61580/61585X1, BU-65170/61580/61585X2, ! BU-65170/61580/61585X3, BU-65170/61580/61585X6 Operating Junction Temperature Storage Temperature Lead Temperature (soldering, 10 sec.) PHYSICAL CHARACTERISTICS Size ! BU-65170/61580/61585 S
! BU-65170/61580/61585 V
0.200 0.630 0.885 1.395
0.25 0.68 1.11 1.97
W W W W
0.850 1.195 1.450 1.975 0.835 1.135 1.435 2.035
1.85 2.25 2.72 3.52 1.67 2.10 2.59 3.46
W W W W W W W W
16.0 12.0 0.01 0.1 0.001 0.01 33 40 2.5 9.5 17.5 18.5 21.5 22.5 49.5 50.5 127 129.5 4 668 19.5 23.5 51.5 131 7 67 60
MHz MHz % % % % % % s s s s s s s s
0.475 0.905 1.160 1.670 0.900 1.245 1.500 2.025 0.885 1.185 1.485 2.085
1.00 1.43 1.86 2.72 2.10 2.50 2.97 3.77 1.92 2.35 2.84 3.71
W W W W W W W W W W W W
0.525 0.955 1.210 1.720
1.25 1.68 2.11 2.97
W W W W
6.99 6.8 -55 -65 150 150 +300
C/W C/W C C C
0.335 0.600 0.860 1.385 0.290 0.590 0.890 1.490
0.68 1.06 1.45 2.23 0.59 0.92 1.36 2.16
W W W W W W W W
1.9 X 1.0 X 0.165 (48.3 x 25.4 x 4.19) 1.9 X 1.0 X 0.150 (48.3 x 25.4 x 3.81) 0.6 (17)
in. (mm) in. (mm) oz (g)
Weight ! BU-65170/61580/61585 S/V
0.200 0.630 0.885 1.395
0.25 0.68 1.11 1.97
W W W W
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BU-65170/61580/61585 H1 web-09/02-0
Notes for Table 1: Notes 1 through 6 are applicable to the Receiver Differential Resistance and Differential Capacitance specifications: (1) Specifications include both transmitter and receiver (tied together internally). (2) Measurement of impedance is directly between pins TX/RX A(B) and TX/RX A(B) of the BU-65170/61580XX hybrid. (3) Assuming the connection of all power and ground inputs to the hybrid. (4) The specifications are applicable for both unpowered and powered conditions. (5) The specifications assume a 2 volt rms balanced, differential, sinusoidal input. The applicable frequency range is 75 kHz to 1 MHz. (6) Minimum resistance and maximum capacitance parameters are guaranteed,but not tested, over the operating range. (7) Assumes a common mode voltage within the frequency range of dc to 2MHz, applied to pins of the isolation transformer on the stub side (either direct or transformer coupled), referenced to hybrid ground. Use a DDC recommended transformer or other transformer that provides an equivalent minimum CMRR. (8) Typical value for minimum intermessage gap time. Under software control, may be lengthened to (65,535s minus message time), in increments of 1s. (9) Software programmable (4 options). Includes RT-to-RT Timeout (Mid-Parity of Transmit Command to Mid-Sync of Transmitting RT Status). (10) For both +5V logic and transceiver. +5V for channels A and B. (11) Measured from mid-parity crossing of Command Word to mid-sync crossing of RT's Status Word. (12) Specifications for BU-65171, BU-61581, and BU-61586 are identical to the specifications for the BU-65170, BU-61580, and BU61585 respectively.
are programmable by subaddress. These features serve to ensure data consistency and to off-load the host processor for bulk data transfer applications. The ACE series implements three monitor modes: a word monitor, a selective message monitor, and a combined RT/selective monitor. Other features include options for automatic retries and programmable intermessage gap for BC mode, an internal Time Tag Register, an Interrupt Status Register and internal command illegalization for RT mode.
FUNCTIONAL OVERVIEW
TRANSCEIVERS
The transceivers in the BU-65170/61580X3(X6) are fully monolithic, requiring only a +5 volt power input. Besides eliminating the need for an additional power supply, the use of a 5 volt (only) transceiver requires the use of step-up, rather than step-down, isolation transformers. This provides the advantage of a higher terminal input impedance than is possible for a 15 volt or 12 volt transmitter. As a result, there is greater margin for the input impedance test, mandated for 1553 validation testing. This allows for longer cable lengths between an LRU's system connector and the isolation transformers of an embedded 1553 terminal. For the +5 V and -15 V/-12 V front end, the BU-65170/ 61580X1(X2) uses low-power bipolar analog monolithic and thick-film hybrid technology. The transceiver requires +5 V and 15 V (-12 V) only (requiring no +15 V/+12 V) and includes voltage source transmitters. The voltage source transmitters provide superior line driving capability for long cables and heavy amounts of bus loading. In addition, the monolithic transceivers in the BU-65170/61580X1 provide a minimum stub voltage level of 20 volts peak-to-peak transformer coupled, making them suitable for MIL-STD-1760 applications. The receiver sections of the BU-65170/61580 are fully compliant with MIL-STD-1553B in terms of front end overvoltage protection, threshold, common mode rejection, and word error rate. In addition, the receiver filters have been designed for optimal operation with the J chip's Manchester II decoders.
INTRODUCTION
DDC's ACE series of Integrated BC/RT/MT hybrids provide a complete, flexible interface between a microprocessor and a MIL-STD-1553A, B Notice 2, McAir, or STANAG 3838 bus, implementing Bus Controller, Remote Terminal (RT) and Monitor Terminal (MT) modes. Packaged in a single 1.9-square-inch, 70-pin DIP or surface mountable flatpack or J-lead package, the ACE series contains dual low-power transceivers and encoder/decoders, complete BC/RT/MT multi-protocol logic, memory management and interrupt logic, 4K x 16 of shared static RAM and a direct, buffered interface to a host processor bus. The BU-65170/61580 contains internal address latches and bidirectional data buffers to provide a direct interface to a host processor bus. The BU-65170/61580 may be interfaced directly to both 16-bit and 8-bit microprocessors in a buffered shared RAM configuration. In addition, the ACE may connect to a 16-bit processor bus via a Direct Memory Access (DMA) interface. The BU-65170/61580 includes 4K words of buffered RAM. Alternatively, the ACE may be interfaced to as much as 64K words of external RAM in either the shared RAM or DMA configurations. The ACE RT mode is multiprotocol, supporting MIL-STD-1553A, MIL-STD-1553B Notice 2, STANAG 3838 (including EFAbus), and the McAir A3818, A5232, and A5690 protocols. Full compliance to the McAir specs, however, requires the use of a sinusoidal transceiver (transceiver option 5). Refer to the BU-61590 data sheet for additional information on McAir terminals. The memory management scheme for RT mode provides an option for separation of broadcast data, in compliance with 1553B Notice 2. Both double buffer and circular buffer options Data Device Corporation www.ddc-web.com
J DIGITAL MONOLITHIC
The J digital monolithic represents the cornerstone element of the ACE family of terminals. The development of the J chip represents the fifth generation of 1553 protocol and interface design for DDC. Over the years, DDC's 1553 protocol and interface design has evolved from: (1) discrete component sets, consisting of multiple hybrids (with large numbers of chips inside the individual hybrids) and programmable logic devices, to (2) multiple custom ASICs to perform the functions of encoder/decoder and RT protocol within a single hybrid, to (3) the BUS-61553 Advanced Integrated Mux Hybrid (AIM-HY) series, containing, in addition to a dual monolithic/thick-film transceiver and discrete RAM chips, a custom protocol chip and a separate custom memory management/processor interface chip, to (4) the BUS-61559 Advanced Integrated Mux Hybrids with Enhanced RT Features (AIM-HY'er -- the AIM-HY'er series includes memory management and processor interface functions beyond those of the AIMHY series) , to (5) the full integration of the J chip. BU-65170/61580/61585 H1 web-09/02-0
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The J chip consists of a dual encoder/decoder, complete protocol for Bus Controller (BC), 1553A/B/McAir Remote Terminal (RT), and Monitor (MT) modes; memory management and interrupt logic; a flexible, buffered interface to a host processor bus and optional external RAM; and 4K words of on-chip RAM. Reference the region within the dotted line of FIGURE 1. Besides realizing all the protocol, memory management, and interface functions of the earlier AIM-HY'er series, the J chip includes a large number of enhancements to facilitate hardware and software design, and to further off-load the 1553 terminal's host processor.
put pin (INT) has three software programmable modes of operation: a pulse, a level output cleared under software control, or a level output automatically cleared following a read of the Interrupt Status Register. Individual interrupts are enabled by the Interrupt Mask Register. The host processor may easily determine the cause of the interrupt by using the Interrupt Status Register. The Interrupt Status Register provides the current state of the interrupt conditions. The Interrupt Status Register may be updated in two ways. In the standard interrupt handling mode, a particular bit in the Interrupt Status Register will be updated only if the condition exists and the corresponding bit in the Interrupt Mask Register is enabled. In the enhanced interrupt handling mode, a particular bit in the Interrupt Status Register will be updated if the condition exists regardless of the contents of the corresponding Interrupt Mask Register bit. In any case, the respective Interrupt Mask Register bit enables an interrupt for a particular condition.
DECODERS
The default mode of operation for the BU-65170 RT and BU61580 BC/RT/MT requires a 16 MHz clock input. If needed, a software programmable option allows the device to be operated from a 12 MHz clock input. Most current 1553 decoders sample using a 10 MHz or 12 MHz clock. In the 16 MHz mode (default following a hardware or software reset), the ACE decoders sample 1553 serial data using the 16 MHz clock. In the 12 MHz mode, the decoders sample using both clock edges; this provides a sampling rate of 24 MHz. The faster sampling rate for the J chip's Manchester II decoders provides superior performance in terms of bit error rate and zero-crossing distortion tolerance. For interfacing to fiber optic transceivers for MIL-STD-1773 applications, a transceiverless version of the J chip, the BU-65620, can be used. These versions provide a pin-programmable option for a direct interface to the single-ended outputs of a fiber optic receiver. No external logic is needed.
ADDRESSING, INTERNAL REGISTERS, AND MEMORY MANAGEMENT
The software interface of the BU-65170/61580 to the host processor consists of 17 internal operational registers for normal operation, an additional 8 test registers, plus 64K x 16 of shared memory address space. The BU-65170/61580's 4K x 16 of internal RAM resides in this address space. Reference TABLE 2 and 24. Definition of the address mapping and accessibility for the ACE's 17 non-test registers, and the test registers, is as follows: Interrupt Mask Register is used to enable and disable interrupt requests for various conditions. Configuration Registers #1 and #2 are used to select the BU61580's mode of operation, and for software control of RT Status Word bits, Active Memory Area, BC Stop-on-Error, RT Memory Management mode selection, and control of the Time Tag operation. Start/Reset Register is used for "command" type functions, such as software reset, BC/MT Start, Interrupt Reset, Time Tag Reset, and Time Tag Register Test. The Start/Reset Register includes provisions for stopping the BC in its auto-repeat mode, either at the end of the current message or at the end of the current BC frame. BC/RT Command Stack Pointer Register allows the host CPU to determine the pointer location for the current or most recent message when the BU-61580 is in BC or RT modes. BC Control Word/RT Subaddress Control Word Register: In BC mode, it allows host access to the current, or most recent BC Control Word. The BC Control Word contains bits that select the active bus and message format, enable off-line self-test, masking of Status Word bits, enable retries and interrupts, and specify MIL-STD-1553A or -1553B error handling. In RT mode, this register allows host access to the current or most recent Subaddress Control Word. The Subaddress Control Word is used to select the memory management scheme and enable interrupts for the current message. The read/write accessibility can be used as an aid for testing the ACE. BU-65170/61580/61585 H1 web-09/02-0
TIME TAGGING
The ACE includes an internal read/writable Time Tag Register. This register is a CPU read/writable 16-bit counter with a programmable resolution of either 2, 4, 8, 16, 32, or 64 s per LSB. Also, the Time Tag Register may be clocked from an external oscillator. Another option allows software-controlled incrementing of the Time Tag Register. This supports self-testing for the Time Tag Register. For each message processed, the value of the Time Tag register is loaded into the second location of the respective descriptor stack entry ("TIME TAG WORD") for both BC and RT modes. Additional provided options will: clear the Time Tag Register following a Synchronize (without data) mode command or load the Time Tag Register following a Synchronize (with data) mode command; enable an interrupt request and a bit setting in the Interrupt Status Register when the Time Tag Register rolls over from 0000 to FFFF. Assuming the Time Tag Register is not loaded or reset, this will occur at approximately 4-second time intervals, for 64 s/LSB resolution, down to 131 ms intervals, for 2 s/LSB resolution. Another programmable option for RT mode is the automatic clearing of the Service Request Status Word bit following the ACE's response to a Transmit Vector Word mode command.
INTERRUPTS
The ACE series components provide many programmable options for interrupt generation and handling. The interrupt outData Device Corporation www.ddc-web.com
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TABLE 2. ADDRESS MAPPING ADDRESS LINES HEX A4 A3 A2 A1 A0 00 01 02 03 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 * * 17 18 * * 1F 1 1 1 1 1 reserved * Not applicable to BU-65170/61571 1 1 0 1 1 0 1 0 1 0 Test Mode Register 7 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Interrupt Mask Register (RD/WR) Configuration Register #1 (RD/WR) Configuration Register #2 (RD/WR) Start/Reset Register (WR) BC/RT Command Stack Pointer Register (RD) BC Control Word*/RT Subaddress Control Word Register (RD/WR) Time Tag Register (RD/WR) Interrupt Status Register (RD) Configuration Register #3 (RD/WR) Configuration Register #4 (RD/WR) Configuration Register #5 (RD/WR) Data Stack Address Register (RD)* BC Frame Time Remaining Register (RD)* BC Time Remaining to Next Message Register (RD)* BC Frame Time*/RT Last Command/MT Trigger Word* Register (RD/WR) RT Status Word Register (RD) RT BIT Word Register (RD) Test Mode Register 0 REGISTER DESCRIPTION/ACCESSIBILITY
Word and BC Block Status Word, additional Stop-On-Error and Stop-OnStatus Set functions, frame auto-repeat, programmable intermessage gap times, automatic retries, expanded Status Word Masking, and the capability to generate interrupts following the completion of any selected message. For RT mode, the enhanced mode features include the expanded RT Block Status Word, the combined RT/Selective Message Monitor mode, internal wrapping of the RTFAIL output signal (from the J chip) to the RTFLAG RT Status Word bit, the double buffering scheme for individual receive (broadcast) subaddresses, and the alternate (fully software programmable) RT Status Word. For MT mode, use of the enhanced mode enables use of the Selective Message Monitor, the combined RT/Selective Monitor modes, and the monitor triggering capability. Data Stack Address Register is used to point to the current address location in shared RAM used for storing message words (second Command Words, Data Words, RT Status Words) in the Selective Word Monitor mode. Frame Time Remaining Register provides a read only indication of the time remaining in the current BC frame. The resolution of this register is 100 s/LSB. Message Time Remaining Register provides a read only indication of the time remaining before the start of the next message in a BC frame. The resolution of this register is 1 s/LSB. BC Frame/RT Last Command/MT Trigger Word Register: In BC mode, it programs the BC frame time, for use in the frame auto-repeat mode. The resolution of this register is 100 s/LSB, with a range of 6.55 seconds; in RT mode, this register stores the current (or most previous) 1553 Command Word processed by the ACE RT; in the Word Monitor mode, this register specifies a 16-bit Trigger (Command) Word. The Trigger Word may be used to start or stop the monitor, or to generate interrupts. Status Word Register and BIT Word Registers provide read-only indications of the BU-65170/61580's RT Status and BIT Words. Test Mode Registers 0-7: These registers may be used to facilitate production or maintenance testing of the BU-65170/61580 and systems incorporating the BU-65170/61580.
TABLE 3. INTERRUPT MASK REGISTER (READ/WRITE 00h)
Time Tag Register maintains the value of a real-time clock. The resolution of this register is programmable from among 2, 4, 8, 16, 32, and 64 s/LSB.The TAG_CLK input signal also may cause an external oscillator to clock the Time Tag Register. Start-of-Message (SOM) and End-ofMessage (EOM) sequences in BC, RT, and Message Monitor modes cause a write of the current value of the Time Tag Register to the stack area of RAM. Interrupt Status Register mirrors the Interrupt Mask Register and contains a Master Interrupt bit. It allows the host processor to determine the cause of an interrupt request by means of a single READ operation. Configuration Registers #3, #4, and #5 are used to enable many of the BU-61580's advanced features. These include all the enhanced mode features; that is, all the functionality beyond that of the previous generation product, the BUS-61559 Advanced Integrated Mux Hybrid with Enhanced RT Features (AIM-HY'er).For all three modes, use of the Enhanced Mode enables the various read-only bits in Configuration Register #1. For BC mode, the enhanced mode features include the expanded BC Control Data Device Corporation www.ddc-web.com
BIT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB)
DESCRIPTION RAM PARITY ERROR BC/RT TRANSMITTER TIMEOUT BC/RT COMMAND STACK ROLLOVER MT COMMAND STACK ROLLOVER MT DATA STACK ROLLOVER HS FAIL BC RETRY RT ADDRESS PARITY ERROR TIME TAG ROLLOVER RT CIRCULAR BUFFER ROLLOVER
BC CONTROL WORD/RT SUBADDRESS CONTROL WORD EOM
15(MSB) RESERVED
BC END OF FRAME FORMAT ERROR
BC STATUS SET/RT MODE CODE/MT PATTERN TRIGGER
END OF MESSAGE
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TABLE 4. CONFIGURATION REGISTER #1 (READ/WRITE 01H) BIT BC FUNCTION (Bits 11-0 Enhanced Mode Only) RT WITHOUT ALTERNATE STATUS (logic 1) (logic 0) CURRENT AREA B/A RT WITH ALTERNATE STATUS (Enhanced Only) (logic 1) (logic 0) CURRENT AREA A/B MONITOR FUNCTION (Enhanced mode only bits 12-0) (logic 0) (logic 1) CURRENT AREA B/A MESSAGE MONITOR ENABLED (MMT) TRIGGER ENABLED WORD START-ON-TRIGGER STOP-ON-TRIGGER NOT USED EXTERNAL TRIGGER ENABLED NOT USED NOT USED NOT USED NOT USED MONITOR ENABLED(Read Only) MONITOR TRIGGERED (Read Only)
15 RT/BC-MT (logic 0) (MSB) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (LSB) MT/BC-RT (logic 0) CURRENT AREA B/A MESSAGE STOP-ON-ERROR FRAME STOP-ON-ERROR
MESSAGE MONITOR ENABLED MESSAGE MONITOR (MMT) ENABLED (MMT) DYNAMIC BUS CONTROL ACCEPTANCE S10 S09 S08 S07 S06 S05 S04 S03 S02 S01 S00
STATUS SET STOP-ON-MESSAGE BUSY STATUS SET STOP-ON-FRAME FRAME AUTO-REPEAT EXTERNAL TRIGGER ENABLED INTERNAL TRIGGER ENABLED INTERMESSAGE GAP TIMER ENABLED RETRY ENABLED DOUBLED/SINGLE RETRY BC ENABLED (Read Only) BC FRAME IN PROGRESS (Read Only) BC MESSAGE IN PROGRESS (Read Only) SERVICE REQUEST SUBSYSTEM FLAG RTFLAG (Enhanced Mode Only) NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED
RT MESSAGE IN PROGRESS RT MESSAGE IN PROGRESS MONITOR ACTIVE (Enhanced mode only,Read Only) (Read Only) (Read Only) TABLE 6. START/RESET REGISTER (WRITE 03H) DESCRIPTION * * * RESERVED BC/MT STOP-ON-MESSAGE BC STOP-ON-FRAME TIME TAG TEST CLOCK TIME TAG RESET INTERRUPT RESET BC/MT START RESET
TABLE 5. CONFIGURATION REGISTER #2 (READ/WRITE 02h) BIT 15(MSB) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) DESCRIPTION ENHANCED INTERRUPTS
RAM PARITY ENABLE (BU-61585/6 AND BU-65621 ONLY)
BIT * * * 7 6 5 4 3 2 1 0(LSB)
15(MSB) RESERVED
BUSY LOOKUP TABLE ENABLE RX SA DOUBLE BUFFER ENABLE OVERWRITE INVALID DATA 256-WORD BOUNDARY DISABLE TIME TAG RESOLUTION 2(TTR2) TIME TAG RESOLUTION 1 (TTR1) TIME TAG RESOLUTION 0 (TTR0) CLEAR TIME TAG ON SYNCHRONIZE LOAD TIME TAG ON SYNCHRONIZE INTERRUPT STATUS AUTO CLEAR LEVEL/PULSE* INTERRUPT REQUEST CLEAR SERVICE REQUEST ENHANCED RT MEMORY MANAGEMENT SEPARATE BROADCAST DATA
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TABLE 7. BC/RT COMMAND STACK POINTER REG. (READ 03H) BIT DESCRIPTION 15(MSB) COMMAND STACK POINTER 15 * * * 0(LSB) * * * COMMAND STACK POINTER 0
BIT * * * 0(LSB)
TABLE 10. TIME TAG REGISTER (READ/WRITE 05H) DESCRIPTION * * * TIME TAG 0
15(MSB) TIME TAG 15
TABLE 8. BC CONTROL WORD REGISTER READ/WRITE 04H, (BU-61580 ONLY) BIT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) DESCRIPTION M.E. MASK SERVICE REQUEST BIT MASK SUBSYS BUSY BIT MASK SUBSYS FLAG BIT MASK TERMINAL FLAG BIT MASK RESERVED BITS MASK RETRY ENABLED BUS CHANNEL A/B OFF LINE SELF TEST MASK BROADCAST BIT EOM INTERRUPT ENABLE 1553A/B SELECT MODE CODE FORMAT BROADCAST FORMAT RT-RT FORMAT 15(MSB) RESERVED
BIT 14 13 12 11 10 9 8 7 6 5 4 3 2 1
TABLE 11. INTERRUPT STATUS REGISTER (READ 06H) DESCRIPTION RAM PARITY ERROR BC/RT TRANSMITTER TIMEOUT BC/RT COMMAND STACK ROLLOVER MT COMMAND STACK ROLLOVER MT DATA STACK ROLLOVER HS FAIL BC RETRY RT ADDRESS PARITY ERROR TIME TAG ROLLOVER RT CIRCULAR BUFFER ROLLOVER
BC CONTROL WORD/RT SUBADDRESS CONTROL WORD EOM
15(MSB) MASTER INTERRUPT
BC END OF FRAME FORMAT ERROR BC STATUS SET/RT MODE CODE/MT PATTERN TRIGGER END OF MESSAGE
0(LSB)
BIT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB)
TABLE 9. RT SUBADDRESS CONTROL WORD (READ/WRITE 04H) DESCRIPTION TX: EOM INT TX: CIRC BUF INT TX: MEMORY MANAGEMENT 2 (MM2) TX: MEMORY MANAGEMENT 1 (MM1) TX: MEMORY MANAGEMENT 0 (MM0) RX: EOM INT RX: CIRC BUF INT RX: MEMORY MANAGEMENT 2 (MM2) RX: MEMORY MANAGEMENT 1 (MM1) RX: MEMORY MANAGEMENT 0 (MM0) BCST: EOM INT BCST: CIRC BUF INT BCST:MEMORY MANAGEMENT 2 (MM2) BCST: MEMORY MANAGEMENT 1 (MM1) BCST: MEMORY MANAGEMENT 0 (MM0)
TABLE 12. CONFIGURATION REGISTER #3 (READ/WRITE 07H) BIT DESCRIPTION 15(MSB) ENHANCED MODE ENABLE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) BC/RT COMMAND STACK SIZE 1 BC/RT COMMAND STACK SIZE 0 MT COMMAND STACK SIZE 1 MT COMMAND STACK SIZE 0 MT DATA STACK SIZE 2 MT DATA STACK SIZE 1 MT DATA STACK SIZE 0 ILLEGALIZATION DISABLED OVERRIDE MODE T/R ERROR ALTERNATE STATUS WORD ENABLE ILLEGAL RX TRANSFER DISABLE BUSY RX TRANSFER DISABLE RTFAIL-FLAG WRAP ENABLE 1553A MODE CODES ENABLE ENHANCED MODE CODE HANDLING
15(MSB) RX: DOUBLE BUFFER ENABLE
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TABLE 13. CONFIGURATION REGISTER #4 (READ/WRITE 08H) BIT DESCRIPTION BIT 15(MSB) EXTERNAL BIT WORD ENABLE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) INHIBIT BIT WORD IF BUSY MODE COMMAND OVERRIDE BUSY EXPANDED BC CONTROL WORD ENABLE BROADCAST MASK ENABLE/XOR RETRY IF -A AND M.E. RETRY IF STATUS SET 1ST RETRY ALT/SAME BUS 2ND RETRY ALT/SAME BUS VALID M.E./NO DATA VALID BUSY/NO DATA MT TAG GAP OPTION LATCH RT ADDRESS WITH CONFIG #5 TEST MODE 2 TEST MODE 1 TEST MODE 0 BIT
TABLE 16. BC FRAME TIME REMAINING REGISTER (READ/WRITE 0BH) DESCRIPTION 15(MSB) BC FRAME TIME REMAINING 15 * * * * * *
0(LSB) BC FRAME TIME REMAINING 0 Note: resolution = 1 s per LSB
TABLE 17. BC MESSAGE TIME REMAINING REGISTER (READ/WRITE 0CH) DESCRIPTION 15(MSB) BC MESSAGE TIME REMAINING 15 * * * 0(LSB) * * * BC MESSAGE TIME REMAINING 0
Note: resolution = 1 s per LSB TABLE 14. CONFIGURATION REGISTER #5 (READ/WRITE 09H) BIT DESCRIPTION 15(MSB) 12MHZ CLOCK SELECT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) LOGIC "0" EXTERNAL TX INHIBIT A, read only BU-65170/61580X6 EXTERNAL TX INHIBIT B, read only BU-65170/61580X6 EXPANDED CROSSING ENABLED RESPONSE TIMEOUT SELECT 1 RESPONSE TIMEOUT SELECT 0 GAP CHECK ENABLED BROADCAST DISABLED RT ADDRESS LATCH/TRANSPARENT (see NOTE) RT ADDRESS 4 RT ADDRESS 3 RT ADDRESS 2 RT ADDRESS 1 RT ADDRESS 0 RT ADDRESS PARITY TABLE 18. BC FRAME TIME/RT LAST COMMAND/T TRIGGER REGISTER (READ/WRITE 0DH) BIT 15(MSB) * * * 0(LSB) DESCRIPTION BIT 15 * * * BIT 0
TABLE 19. RT STATUS WORD REGISTER (READ/WRITE 0EH) BIT DESCRIPTION 15(MSB) LOGIC "0" 14 13 12 11 10 9 8 7 LOGIC "0" LOGIC "0" LOGIC "0" LOGIC "0" MESSAGE ERROR INSTRUMENTATION SERVICE REQUEST RESERVED RESERVED RESERVED BROADCAST COMMAND RECEIVED BUSY SUBSYSTEM FLAG DYNAMIC BUS CONTROL ACCEPT TERMINAL FLAG
Notes for TABLE 14: Read only, logic "0" for 65170/61580, logic "1" for 65171/61581/61586.
TABLE 15. MONITOR DATA STACK ADDRESS REGISTER (READ/WRITE 0AH) BIT DESCRIPTION 15(MSB) MONITOR DATA STACK ADDRESS 15 * * * 0(LSB) * * * MONITOR DATA STACK ADDRESS 0
6 5 4 3 2 1 0(LSB)
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BIT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB)
TABLE 20. RT BIT WORD REGISTER (READ 0FH) DESCRIPTION LOOP TEST FAILURE B LOOP TEST FAILURE A HANDSHAKE FAILURE TRANSMITTER SHUTDOWN B TRANSMITTER SHUTDOWN A TERMINAL FLAG INHIBITED CHANNEL B/A HIGH WORD COUNT LOW WORD COUNT INCORRECT SYNC RECEIVED PARITY/MANCHESTER ERROR RECEIVED RT-RT GAP/SYNCH/ADDRESS ERROR RT-RT NO RESPONSE ERROR RT-RT 2ND COMMAND WORD ERROR COMMAND WORD CONTENTS ERROR NOTE: TABLES 21 TO 24 ARE NOT REGISTERS, BUT THEY ARE WORDS STORED IN RAM. TABLE 21. BC MODE BLOCK STATUS WORD DESCRIPTION SOM CHANNEL B/A ERROR FLAG STATUS SET FORMAT ERROR NO RESPONSE TIMEOUT LOOP TEST FAIL MASKED STATUS SET RETRY COUNT 1 RETRY COUNT 0 GOOD DATA BLOCK TRANSFER WRONG STATUS ADDRESS/NO GAP WORD COUNT ERROR INCORRECT SYNC TYPE INVALID WORD
BIT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB)
TABLE 22. RT MODE BLOCK STATUS WORD DESCRIPTION SOM CHANNEL B/A ERROR FLAG RT-RT FORMAT FORMAT ERROR NO RESPONSE TIMEOUT LOOP TEST FAIL DATA STACK ROLLOVER ILLEGAL COMMAND WORD WORD COUNT ERROR INCORRECT SYNC INVALID WORD RT-RT GAP/SYNC/ADDRESS ERROR RT-RT 2ND COMMAND ERROR COMMAND WORD CONTENTS ERROR TABLE 23. WORD MONITOR IDENTIFICATION WORD DESCRIPTION * * * GAP TIME WORD FLAG THIS RT BROADCAST ERROR COMMAND/DATA CHANNEL B/A CONTIGUOUS DATA/GAP MODE CODE
15(MSB) TRANSMITTER TIMEOUT
15(MSB) EOM
BIT * * * 8 7 6 5 4 3 2 1
15(MSB) GAP TIME
BIT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB)
15(MSB) EOM
0(LSB)
TABLE 24. MESSAGE MONITOR MODE BLOCK STATUS WORD BIT DESCRIPTION 15(MSB) EOM 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) SOM CHANNEL B/A ERROR FLAG RT-RT TRANSFER FORMAT ERROR NO RESPONSE TIMEOUT GOOD DATA BLOCK TRANSFER DATA STACK ROLLOVER RESERVED WORD COUNT ERROR INCORRECT SYNC INVALID WORD RT-RT GAP/SYNC/ADDRESS ERROR RT-RT 2ND COMMAND ERROR COMMAND WORD CONTENTS ERROR
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BUS CONTROLLER (BC) ARCHITECTURE
The BC protocol of the BU-61580 implements all MIL-STD1553B message formats. Message format is programmable on a message-by-message basis by means of bits in the BC Control Word and the T/R bit of the Command Word for the respective message. The BC Control Word allows 1553 message format, 1553A/B type RT, bus channel, self-test, and Status Word masking to be specified on an individual message basis. In addition, automatic retries and/or interrupt requests may be enabled or disabled for individual messages. The BC performs all error checking required by MIL-STD-1553B. This includes validation of response time, sync type and sync encoding, Manchester II encoding, parity, bit count, word count, Status Word RT Address field, and various RT-to-RT transfer errors. The BU-61580's BC response timeout value is programmable with choices of 18, 22, 50, and 130 s. The longer response timeout values enable operation over long buses and/or the use of repeaters. FIGURE 2 illustrates BC intermessage gap and frame timing. The BU-61580 may be programmed to process BC frames of up to 512 messages with no processor intervention. It is possible to program for either single frame or frame auto-repeat operation. In the auto-repeat mode, the frame repetition rate may be controlled either internally, using a programmable BC frame timer, or from an external trigger input. The internal BC frame time is programmable up to 6.55 seconds in increments of 100 s. In addition to BC frame time, intermessage gap time, measured from the start of the current message to the start of the subsequent message, is programmable on an individual message basis. The time between individual successive messages is programmable up to 65.5 ms, in increments of 1 s.
TABLE 25. TYPICAL BC MEMORY ORGANIZATION (SHOWN FOR 4K RAM) ADDRESS DESCRIPTION (HEX) 0000-00FF 0100 0101 0102 0103 0104 0105 0106 0107 0108-012D 012E-0153 0154-0179 * * * 0ED6-0EFB 0EFC-0EFF 0F00-0FFF Stack A Stack Pointer A (fixed location) Message Count A (fixed location) Initial Stack Pointer A (see note) (Auto-Frame Repeat Mode) Initial Message Count A (see note) (Auto-Frame Repeat Mode) Stack Pointer B Message Count B Initial Stack Pointer B (see note) (Auto-Frame Repeat Mode) Initial Message Count B (see note) (Auto-Frame Repeat Mode) Message Block 0 Message Block 1 Message Block 2 * * * Message Block 93 Not Used Stack B
BC MEMORY ORGANIZATION
TABLE 25 illustrates a typical memory map for BC mode. It is important to note that the only fixed locations for the BU-61580 in the Standard BC mode are for the two Stack Pointers (address locations 0100 (hex) and 0104) and for the two Message Count locations (0101 and 0105). Enabling the Frame Auto-Repeat mode will reserve four more memory locations for use in the Enhanced BC mode; these locations are for the two Initial Stack Pointers (address locations 102 (hex) and 106) and for the Initial Message Count locations (103 and 107). The user is free to
Note: Used only in the Enhanced BC mode with Frame Auto-Repeat enabled.
locate the Stack and BC Message Blocks anywhere else within the 64K (4K internal) shared RAM address space. For simplicity of illustration, assume the allocation of the maximum length of a BC message for each message block in the typical BC memory map of TABLE 25. The maximum size of a BC message block is 38 words, for an RT-to-RT transfer of 32 Data Words (Control + 2 Commands + Loopback + 2 Status Words + 32 Data Words). Note, however, that this example assumes the disabling of the 256-word boundaries.
MESSAGE GAP TIME FOR MESSAGE NO. 1 INTERMESSAGE GAP TIME
MESSAGE NO. 1
MESSAGE NO. 2
MESSAGE NO. 1
BC FRAME TIME
FIGURE 2. BC MESSAGE GAP AND FRAME TIMING
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BC MEMORY MANAGEMENT
FIGURE 3 illustrates the BU-61580's BC memory management scheme. One of the BC memory management features is the global double buffering mechanism. This provides for two sets of the various BC mode data structures: Stack Pointer and Message Counter locations, Descriptor Stack areas, and BC message blocks. Bit 13 of Configuration Register #1 selects the current active area. At any point in time, the BU-61580's internal 1553 memory management logic may access only the various data structures within the "active" area. FIGURE 3 delineates the "active" and "inactive" areas by the nonshaded and shaded areas, respectively; however, at any point in time, both the "active" and "nonactive" areas are accessible by the host processor. In most applications, the host processor will access the "nonactive" area, while the 1553 bus processes the "active" area messages. The BC may be programmed to transmit multimessage frames of up to 512 messages. The number of messages to be processed is programmable by the Active Area Message Count location in the shared RAM, initialized by the host processor. In addition, the host processor must initialize another location, the Active Area Stack Pointer. The Stack Pointer references the four-word message block descriptor in the Stack area of shared RAM for each message to be processed. The BC Stack size is programmable with choices of 256, 512, 1024, and 2048 words. In the BC Frame Auto-Repeat mode, the Initial Stack Pointer and Initial Message Counter locations must be loaded by the host
prior to the processing of the first frame. The single frame mode does not use these two locations. The third and fourth words of the BC block descriptor are the Intermessage Gap Time and the Message Block Address for the respective message. These two memory locations must be written by the host processor prior to the start of message processing. Use of the Intermessage Gap Time is optional. The Block Address pointer specifies the starting location for each message block. The first word of each BC message block is the BC Control Word. At the start and end of each message, the Block Status and Time Tag Words write to the message block descriptor in the stack. The Block Status Word includes indications of message in process or message completion, bus channel, status set, response timeout, retry count, status address mismatch, loop test (on-line self-test) failure, and other error conditions. TABLE 21 illustrates the bit mapping of the BC Block Status word. The 16-bit Time Tag Word will reflect the current contents of the internal Time Tag Register. This read/writable register, which operates for all three modes, has programmable resolution of from 2 to 64 s/LSB. In addition, the Time Tag register may be clocked from an external source.
BC MESSAGE BLOCK FORMATS AND BC CONTROL WORD
In BC mode, the BU-61580 supports all MIL-STD-1553 message formats. For each 1553 message format, the BU-61580 mandates a specific sequence of words within the BC Message
INITIAL STACK POINTERS (NOTE) MESSAGE BLOCKS
CONFIGURATION REGISTER 1
15
13
0
STACK POINTERS
DESCRIPTOR STACKS
CURRENT AREA B/A INITIAL MESSAGE COUNTERS (NOTE)
BLOCK STATUS WORD TIME TAG WORD MESSAGE GAP TIME WORD MESSAGE BLOCK ADDR MESSAGE BLOCK
MESSAGE COUNTERS
MESSAGE BLOCK
NOTE: INITIAL STACK POINTERS AND INITIAL MESSAGE COUNTERS USED ONLY IN BC FRAME AUTO-REPEAT MODE.
FIGURE 3. BC MODE MEMORY MANAGEMENT
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Block. This includes locations for the Control, Command and (transmitted) Data Words that are to be read from RAM by the BC protocol logic. In addition, subsequent contiguous locations must be allocated for storage of received Loopback, RT Status and Data Words. FIGURE 4 illustrates the organization of the BC message blocks for the various MIL-STD-1553 message formats. Note that for all of the message formats, the BC Control Word is located in the first location of the message block.
BC-to-RT Transfer Control Word Receive Command Word Data Word #1 Data Word #2 . . . Last Data Word Last Data Word Looped Back Status Received RT-to-RT Transfer Control Word Receive Command Transmit Command Transmit Command Looped Back Tx RT Status Word Data #1 Data #2 . . . Last Data Rx RT Status Word Rx Mode Code; With Data Control Word Rx Mode Command Data Word Data Word Looped Back Status Received Broadcast Control Word Broadcast Command Data #1 Data #2 . . . Last Data Last Data Status Word RT-to-RTs (Broadcast) Transfer Control Word Rx Broadcast Command Tx Command Tx Command Looped Back Tx RT Status Word Data #1 Data #2 . . . Last Data Broadcast Mode Code; No Data Control Word Broadcast Mode Command Broadcast Mode Command Looped Back Broadcast Mode Code; With Data Control Word Broadcast Mode Command Data Word Data Word Looped Back Mode Code; No Data Control Word Mode Command Mode Command Looped Back Status Received RT-to-BC Transfer Control Word Transmit Command Word Transmit Command Looped Back Status Received Data Word #1 Data Word #2 . . . Last Data Word Tx Mode Code; With Data Control Word Tx Mode Command Mode Command Looped Back Status Received Data Word
For each of the BC Message Block formats, the first word in the block is the BC Control Word. The BC Control Word is not transmitted on the 1553 bus. Instead, it contains bits that select the active bus and message format; enable off-line self-test; masking of Status Word bits; enable retries and interrupts; and specifies MIL-STD-1553A or -1553B error handling. The bit mapping and definitions of the BC Control Word are illustrated in TABLE 8. The BC Control Word is followed by the Command Word to be transmitted, and subsequently by a second Command Word (for an RT-to-RT transfer), followed by Data Words to be transmitted (for Receive commands). The location after the last word to be transmitted is reserved for the Loopback Word. The Loopback Word is an on-line self-test feature. The subsequent locations after the Loopback Word are reserved for received Status Words and Data Words (for Transmit commands).
AUTOMATIC RETRIES
The BU-61580 BC implements automatic message retries. When enabled, retries will occur, following response timeout or format error conditions. As additional options, retries may be enabled when the Message Error Status Word bit is set by a 1553A RT or following a "Status Set" condition. For a failed message, either one or two message retries will occur, the bus channel (same or alternate) is independently programmable for the first and second retry attempts. Retries may be enabled or disabled on an individual message basis.
BC INTERRUPTS
BC interrupts may be enabled by the Interrupt Mask Register for Stack Rollover, Retry, End-of-Message (global), End-ofMessage (in conjunction with the BC Control Word for individual messages), response timeout, message error, end of BC frame, and Status Set conditions. The definition of "Status Set" is programmable on an individual message basis, by means of the BC Control Word. This allows for masking ("care/don't care") of the individual RT Status Word bits.
REMOTE TERMINAL (RT) ARCHITECTURE
The RT protocol design of the BU-65170/61580 represents DDC's fifth generation implementation of a 1553 RT. One of the salient features of the ACE's RT architecture is its true multiprotocol functionality. This includes programmable options for support of MIL-STD-1553A, the various McAir protocols, and MILSTD-1553B Notice 2. The BU-65170/61580 RT response time is 2 to 5 s dead time (4 to 7 s per 1553B), providing compliance to all the 1553 protocols. Additional multiprotocol features of the BU-65170/61580 include options for full software control of RT Status and Built-in-Test (BIT) words. Alternatively, for 1553B applications, these words may be formulated in real time by the BU-65170/61580 protocol logic. The BU-65170/61580 RT protocol design implements all the MIL-STD-1553B message formats and dual redundant mode codes. This design is based largely on previous generation products that have passed SEAFAC testing for MIL-STD-1553B compliance. The ACE RT performs comprehensive error checking, word and format validation, and checks for various RT-to-RT transfer errors. Other key features of the BU-65170/61580 RT BU-65170/61580/61585 H1 web-09/02-0
FIGURE 4. BC MESSAGE BLOCK FORMATS
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include a set of interrupt conditions, internal command illegalization, and programmable busy by subaddress.
TABLE 26. TYPICAL RT MEMORY MAP (SHOWN FOR 4K RAM) ADDRESS (HEX) 0000-00FF 0100 0101-0103 0104 0105-0107 0108-010F 0110-013F 0140-01BF 01C0-023F 0240-0247 0248-025F 0260-027F 0280-02FF 0300-03FF 0400-041F 0420-043F ** * * 0FE0-0FFF DESCRIPTION Stack A Stack Pointer A (fixed location) RESERVED Stack Pointer B (fixed location) RESERVED Mode Code Selective Interrupt Table (fixed area) Mode Code Data (fixed area) Lookup Table A (fixed area) Lookup Table B (fixed area) Busy Bit Lookup Table (fixed area) (not used) Data Block 0 Data Block 1-4 Command Illegalizing Table (fixed area) Data Block 5 Data Block 6 * * * Data Block 100 TABLE 27. LOOK-UP TABLES AREA A 0140 . . . 015F 0160 . . . 017F 0180 . . . 019F 01A0 . . . 01BF AREA B 01C0 . . . 01DF 01E0 . . . 01FF 0200 . . . 021F 0220 . . . 023F DESCRIPTION Rx(/Bcst)_SA0 . . . Rx(/Bcst)_SA31 Tx_SA0 . . . Tx_SA31 Bcst_SA0 . . . Bcst_SA31 SACW_SA0 . . . SACW_SA31 COMMENT Receive (/Broadcast) Lookup Table
RT MEMORY ORGANIZATION
TABLE 26 illustrates a typical memory map for the BU-61580 in RT mode. As in BC mode, the two Stack Pointers reside in fixed locations in the shared RAM address space: address 0100 (hex) for the Area A Stack Pointer and address 0104 for the Area B Stack Pointer. Besides the Stack Pointer, for RT mode there are several other areas of the ACE address space designated as fixed locations. All RT modes of operation require the Area A and Area B Lookup Tables. Also allocated are several fixed locations for optional features: Command Illegalization Lookup Table, Mode Code Selective Interrupt Table, Mode Code Data Table, and Busy Bit Lookup Table. It should be noted that any unenabled optional fixed locations may be used for general purpose storage (data blocks). The RT Lookup tables, which provide a mechanism for mapping data blocks for individual Tx/Rx/Bcst-subaddresses to areas in the RAM, occupy address range locations are 0140 to 01BF for Area A and 01C0 to 023F for Area B. The RT lookup tables include Subaddress Control Words and the individual Data Block Pointers. If used, address range 0300-03FF will be dedicated as the illegalizing section of RAM. The actual Stack RAM area and the individual data blocks may be located in any of the nonfixed areas in the shared RAM address space.
RT MEMORY MANAGEMENT
One of the salient features of the ACE series products is the flexibility of its RT memory management architecture. The RT architecture allows the memory management scheme for each transmit, receive, or broadcast subaddress to be programmable on a subaddress basis. Also, in compliance with MIL-STD-1553B Notice 2, the BU-65170/61580 provides an option to separate data received from broadcast messages from nonbroadcast received data. Besides supporting a global double buffering scheme (as in BC mode), the ACE RT provides a pair of 128-word Lookup Tables for memory management control. They are programmable on a subaddress basis (refer to TABLE 27). These 128-word tables include 32-word tables for transmit message pointers and receive message pointers. There is also a third, optional Lookup Table for broadcast message pointers, providing Notice 2 compliance, if necessary. The fourth section of each of the RT Lookup Tables stores the 32 Subaddress Control Words (refer to TABLE 9 and 28). The individual Subaddress Control Words may be used to select the RT memory management option and interrupt scheme for each transmit, receive, and (optionally) broadcast subaddress. For each transmit subaddress, there are two possible memory management schemes: (1) single message; and (2) circular buffer. For each receive (and optionally broadcast) subaddress, there are three possible memory management schemes: (1) single message; (2) double buffered; and (3) circular buffer. For each transmit, receive and broadcast subaddress, there are two interrupt conditions that are programmable by the respective Subaddress Control Word: (1) after every message to the subData Device Corporation www.ddc-web.com
Transmit Lookup Table
Broadcast Lookup Table Optional
Subaddress Control Word Lookup Table (Optional)
TABLE 28. SUBADDRESS CONTROL WORD Memory Management Subaddress Buffer Scheme MM2 0 0 0 0 1 1 1 1 MM1 0 0 1 1 0 0 1 1 MM0 0 1 0 1 0 1 0 1 DESCRIPTION 128-Word 256-Word 512-Word 1024-Word 2048-Word 4096-Word 8192-Word COMMENT Circular Buffer of Specified Size Single Message or Double Buffered
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address; (2) after a circular buffer rollover. An additional table in RAM may be used to enable interrupts following selected mode code messages. When using the circular buffer scheme for a given subaddress, the size of the circular buffer is programmable by three bits of the Subaddress Control Word (see TABLE 28). The options for circular buffer size are 128, 256, 512, 1024, 2048, 4096, and 8192 Data Words.
SINGLE MESSAGE MODE
FIGURE 5 illustrates the RT Single Message memory management scheme. When operating the BU-65170/61580 in its "AIMHY" (default) mode, the Single Message scheme is implemented for all transmit, receive, and broadcast subaddresses. In the Single Message mode (also in the Double Buffer and Circular Buffer modes), there is a global double buffering scheme, controlled by bit 13 of Configuration Register #1. This selects from between the two sets of the various data structures shown in the figure: the Stack Pointers (fixed addresses), Descriptor Stacks (user defined addresses), RT Lookup Tables (fixed addresses), and RT Data Word blocks (user defined addresses). FIGURES 5, 6, and 7 delineate the "active" and "nonactive" areas by the nonshaded and shaded areas, respectively. As shown, the ACE stores the Command Word from each message received, in the fourth location within the message descriptor (in the stack) for the respective message. The T/R bit, subaddress field, and (optionally) broadcast/own address, index into the active area Lookup Table, to locate the data block pointer for the current message. The BU-65170/61580 RT memory management logic then accesses the data block pointer to locate the starting address for the Data Word block for the current message. The maximum size for an RT Data Word block is 32 words. For a particular subaddress in the Single Message mode, there is overwriting of the contents of the data blocks for receive/broadcast subaddresses -- or overreading, for transmit subaddresses. In the single message mode, it is possible to access multiple data blocks for the same subaddress. This, however, requires the intervention of the host processor to update the respective Lookup Table pointer. To implement a data wraparound subaddress, as required by Notice 2 of MIL-STD-1553B, the Single Message scheme should be used for the wraparound subaddress. Notice 2 recommends subaddress 30 as the wraparound subaddress.
At the end of a valid (or optionally invalid) message, the value of the Lookup Table entry updates to the next location after the last address accessed for the current message. As a result, Data Words for the next message directed to the same Tx/RX(/Bcst) subaddress will be accessed from the next contiguous block of address locations within the circular buffer. As a recommended option, the Lookup Table pointers may be programmed to not update following an invalid receive (or broadcast) message. This allows the 1553 bus controller to retry the failed message, resulting in the valid (retried) data overwriting the invalid data. This eliminates overhead for the RT's host processor. When the pointer reaches the lower boundary of the circular buffer (located at 128, 256, . . . 8192-word boundaries in the BU-65170/61580 address space), the pointer moves to the top boundary of the circular buffer, as FIGURE 6 shows. Implementing Bulk Data Transfers The use of the Circular Buffer scheme is ideal for bulk data transfers; that is, multiple messages to/from the same subaddress. The recommendation for such applications is to enable the circular buffer interrupt request. By so doing, the routine transfer of multiple messages to the selected subaddress, including errors and retries, is transparent to the RT's host processor. By strategically initializing the subaddresses' Lookup Table pointer prior to the start of the bulk transfer, the BU-65170/61580 may be configured to issue an interrupt request only after it has received the anticipated number of valid Data Words to the designated subaddress.
SUBADDRESS DOUBLE BUFFERING MODE
For receive (and broadcast) subaddresses, the BU-65170/61580 RT offers a third memory management option, Subaddress Double Buffering. Subaddress Double Buffering provides a means of ensuring data consistency. FIGURE 7 illustrates the RT Subaddress Double Buffering scheme. Like the Single Message and Circular Buffer modes, the Double Buffering mode may be selected on a subaddress basis by means of the Subaddress Control Word. The purpose of the Double Buffering mode is to provide the host processor a convenient means of accessing the most recent, valid data received to a given subaddress. This serves to ensure the highest possible degree of data consistency by allocating two 32-bit Data Word blocks for each individual receive (and/or broadcast) subaddress. At a given point in time, one of the two blocks will be designated as the "active" 1553 data block while the other will be designated as the "inactive" block. The Data Words from the next receive message to that subaddress will be stored in the "active" block. Upon completion of the message, provided that the message was valid and Subaddress Double Buffering is enabled, the BU65170/61580 will automatically switch the "active" and "inactive" blocks for the respective subaddress. The ACE accomplishes this by toggling bit 5 of the subaddress's Lookup Table Pointer and rewriting the pointer. As a result, the most recent valid block of received Data Words will always be readily accessible to the host processor. As a means of ensuring data consistency, the host processor is able to reliably access the most recent valid, received Data Word block by performing the following sequence: BU-65170/61580/61585 H1 web-09/02-0
CIRCULAR BUFFER MODE
FIGURE 6 illustrates the RT circular buffer memory management scheme. The circular buffer mode facilitates bulk data transfers. The size of the RT circular buffer, shown on the right side of the figure, is programmable from 128 to 8192 words (in even powers of 2) by the respective Subaddress Control Word. As in the single message mode, the host processor initially loads the individual Lookup Table entries. At the start of each message, the ACE stores the Lookup Table entry in the third position of the respective message block descriptor in the stack area of RAM, as in the Single Message mode. The ACE transfers Receive or Transmit Data Words to (from) the circular buffer, starting at the location referenced by the Lookup Table pointer. Data Device Corporation www.ddc-web.com
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CONFIGURATION REGISTER
STACK POINTERS
DESCRIPTOR STACKS
LOOK-UP TABLE (DATA BLOCK ADDR)
15
13
0
DATA BLOCKS
CURRENT AREA B/A
BLOCK STATUS WORD TIME TAG WORD DATA BLOCK POINTER RECEIVED COMMAND WORD LOOK-UP TABLE ADDR (See note)
DATA BLOCK
DATA BLOCK
Note: Lookup table is not used for mode commands when enchanced mode codes are enabled.
FIGURE 5. RT MEMORY MANAGEMENT: SINGLE MESSAGE MODE
CONFIGURATION REGISTER STACK POINTERS DESCRIPTOR STACK LOOK-UP TABLES CIRCULAR DATA BUFFER
15
13
0
CURRENT AREA B/A BLOCK STATUS WORD TIME TAG WORD DATA BLOCK POINTER RECEIVED COMMAND WORD LOOK-UP TABLE ADDRESS POINTER TO CURRENT DATA BLOCK LOOK-UP TABLE ENTRY POINTER TO NEXT DATA BLOCK * RECEIVED (TRANSMITTED) MESSAGE DATA (NEXT LOCATION)
128, 256
8192 WORDS
* TX/RS/BCST_SA LOOK-UP TABLE ENTRY IS UPDATED
FOLLOWING VALID RECEIVE (BROADCAST) MESSAGE OR FOLLOWING COMPLETION OF TRANSIT MESSAGE.
CIRCULAR BUFFER ROLLOVER
FIGURE 6. RT MEMORY MANAGEMENT: CIRCULAR BUFFER MODE
CONFIGURATION REGISTER STACK POINTERS DESCRIPTOR STACK LOOK-UP TABLES
15
13
0
DATA BLOCKS
CURRENT AREA B/A BLOCK STATUS WORD X..X 0 YYYYY TIME TAG WORD DATA BLOCK POINTER RECEIVED COMMAND WORD DATA BLOCK POINTER X..X 1 YYYYY DATA BLOCK 1 DATA BLOCK 0
RECEIVE DOUBLE BUFFER ENABLE MSB SUBADDRESS CONTROL WORD
FIGURE 7. RT MEMORY MANAGEMENT: SUBADDRESS DOUBLE BUFFERING MODE
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(1) Disable the double buffering for the respective subaddress by the Subaddress Control Word. That is, temporarily switch the subaddress' memory management scheme to the Single Message mode. (2) Read the current value of the receive (or broadcast) subaddress's Lookup Table pointer. This points to the current "active" Data Word block. By inverting bit 5 of this pointer value, it is possible to locate the start of the "inactive" Data Word block. This block will contain the Data Words received during the most recent valid message to the subaddress. (3) Read out the words from the "inactive" (most recent) Data Word Block. (4) Re-enable the Double Buffering mode for the respective subaddress by the Subaddress Control Word.
the need for an external PROM, PLD, or RAM device that does the illegalizing function. The BU-J1165170/61580's illegalization scheme provides maximum flexibility, allowing any subset of the 4096 possible combinations of broadcast/own address, T/R bit, subaddress, and word count/mode code to be illegalized. Another advantage of the RAM-based illegalization technique is that it provides for a high degree of self-testability. Addressing the Illegalization Table TABLE 29 illustrates the addressing scheme of the illegalization RAM. As shown, the base address of the illegalizing RAM is 0300 (hex). The ACE formulates the index into the Illegalizing Table based on the values of BROADCAST/OWN ADDRESS, T/R bit, Subaddress, and the MSB of the Word Count/Mode Code field (WC/MC4) of the current Command Word. The internal RAM has 256 words reserved for command illegalization. Broadcast commands may be illegalized separately from nonbroadcast receive commands and mode commands. Commands may be illegalized down to the word count level. For example, a one-word receive command to subaddress 1 may be legal, while a two-word receive command to subaddress 1 may be illegalized. The first 64 words of the Illegalization Table refer to broadcast receive commands (two words per subaddress). The next 64 words refer to broadcast transmit commands. Since nonmode code broadcast transmit commands are by definition invalid, this section of the table (except for subaddresses 0 and 31) does not need to be initialized by the user. The next 64 words correspond to nonbroadcast receive commands. The final 64 words refer to nonbroadcast transmit commands. Messages with Word Count/ Mode Code (WC/MC) fields between 0 and 15 may be illegalized by setting the corresponding data bits for the respective evennumbered address locations in the illegalization table. Likewise, messages with WC/MC fields between 16 and 31 may be illegalized by setting the corresponding data bits for the respective odd-numbered address locations in the illegalization table. The following should be noted with regards to command illegalization: (1)To illegalize a particular word count for a given broadcast/own address-T/R subaddress, the appropriate bit position in the respective illegalization word should be set to logic 1. A bit value of logic 0 designates the respective Command Word as a legal command. The ACE will respond to an illegalized nonbroadcast command with the Message Error bit set in its RT Status Word. (2)For subaddresses 00001 through 11110, the "WC/MC" field specifies the Word Count field of the respective Command Word. For subaddresses 00000 and 11111, the "WC/MC" field specifies the Mode Code field of the respective Command Word. (3)Since nonmode code broadcast transmit messages are not defined by MIL-STD-1553B, the sixty (60) words in the illegalization RAM, addresses 0342 through 037D, corresponding to these commands do not need to be initialized. The ACE will not respond to a nonmode code broadcast transmit command, but will automatically set the Message BU-65170/61580/61585 H1 web-09/02-0
RT INTERRUPTS
As in BC mode, the BU-65170/61580 RT provides many maskable interrupts. RT interrupt conditions include End of (every) Message, Message Error, Selected Subaddress (Subaddress Control Word) Interrupt, Circular Buffer Rollover, Selected Mode Code Interrupt, and Stack Rollover.
DESCRIPTOR STACK
At the beginning and end of each message, the BU65170/61580 RT stores a four-word message descriptor in the active area stack. The RT stack size is programmable, with choices of 256, 512, 1024, and 2048 words. FIGURES 5, 6 and 7 show the four words: Block Status Word, Time Tag Word, Data Block Pointer, and the 1553 received Command Word. The RT Block Status Word includes indications of message in-progress or message complete, bus channel, RT-to-RT transfer and RT-toRT transfer errors, message format error, loop test (self-test) failure, circular buffer rollover, illegal command, and other error conditions. TABLE 22 shows the bit mapping of the RT Block Status Word. As in BC mode, the Time Tag Word stores the current contents of the BU-65170/61580's read/writable Time Tag Register. The resolution of the Time Tag Register is programmable from among 2, 4, 8, 16, 32, and 64 s/LSB. Also, incrementing of the Time Tag counter may be from an external clock source or via software command. The ACE stores the contents of the accessed Lookup Table location for the current message, indicating the starting location of the Data Word block, as the Data Block Pointer. This serves as a convenience in locating stored message data blocks. The ACE stores the full 16-bit 1553 Command Word in the fourth location of the RT message descriptor.
RT COMMAND ILLEGALIZATION
The BU-65170/61580 provides an internal mechanism for RT command illegalization. In addition, the Busy Status Word bit can be set so that it is only a programmed subset of the transmit/receive/broadcast subaddresses. The illegalization scheme uses a 256-word area in the BU65170/61580's address space. A benefit of this feature is the reduction of printed circuit board requirements, by eliminating
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TABLE 29. ILLEGALIZATION RAM ADDRESS DEFINITION BIT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) DESCRIPTION 0 0 0 0 0 1 1 BROADCAST/OWN_ADDRESS T/R SA4 SA3 SA2 SA1 SA0 WC4/MC4 15(MSB) 0
The strong recommendation for new applications is the use of the Selective Message Monitor, rather than the Word Monitor. Besides providing monitor filtering based on RT Address, T/R bit, and Subaddress, the Message Monitor eliminates the need to determine the start and end of messages by software. The development of such software tends to be a tedious task. Moreover, at run time, it tends to entail a high degree of CPU overhead.
WORD MONITOR
In the Word Monitor mode, the BU-61580 monitors both 1553 buses. After initializing the Word Monitor and putting it on-line the BU-61580 stores all Command, Status, and Data Words received from both buses. For each word received from either bus, the BU-61580 stores a pair of words in RAM. The first word is the 16 bits of data from the received word. The second word is the Monitor Identification (ID), or "Tag" word. The ID Word contains information relating to bus channel, sync type, word validity, and interword time gaps. The BU-61580 stores data and ID words in a circular buffer in the shared RAM address space. TABLE 23 shows the bit mapping for the Monitor ID word.
Error bit in its internal Status Register, regardless of whether or not corresponding bit in the illegalization RAM has been set. If the next message is a Transmit Status or Transmit Last Command mode code, the ACE will respond with its Message Error bit set.
MONITOR TRIGGER WORD
There is a Trigger Word Register that provides additional flexibility for the Word Monitor mode. The BU-61580 stores the value of the 16-bit Trigger Word in the MT Trigger Word Register. The contents of this register represent the value of the Trigger Command Word. The BU-61580 has programmable options to start or stop the Word Monitor, and/or to issue an interrupt request following receipt of the Trigger Command Word from the 1553 bus.
PROGRAMMABLE BUSY
As a means of providing compliance with Notice 2 of MIL-STD1553B, the BU-65170/61580 RT provides a software controllable means for setting the Busy Status Word bit as a function of subaddress. By a Busy Lookup Table in the BU-65170/61580 address space, it is possible to set the Busy bit based on command broadcast/own address, T/R bit, and subaddress. Another programmable option, allows received Data Words to be either stored or not stored for messages, when the Busy bit is set.
SELECTIVE MESSAGE MONITOR MODE
The BU-61580 Selective Message Monitor provides features to greatly reduce the software and processing burden of the host CPU. The Selective Message Monitor implements selective monitoring of messages from a dual 1553 bus, with the monitor filtering based on the RT Address, T/R bit, and Subaddress fields of received 1553 Command Words. The Selective Message Monitor mode greatly simplifies the host processor software by distinguishing between Command and Status Words. The Selective Message Monitor maintains two stacks in the BU61580 RAM: a Command Stack and a Data Stack. Simultaneous RT/Message Monitor Mode The Selective Message Monitor may function as a purely passive monitor or may be programmed to function as a simultaneous RT/Monitor. The RT/Monitor mode provides complete Remote Terminal (RT) operation for the BU-61580's strapped RT address and bus monitor capability for the other 30 nonbroadcast RT addresses. This allows the BU-61580 to simultaneously operate as a full function RT and "snoop" on all or a subset of the bus activity involving the other RTs on a bus. This type of operation is sometimes needed to implement a backup bus controller. The combined RT/Selective Monitor maintains three stack areas in the BU-61580 address space: an RT Command Stack, a Monitor Command Stack, and a Monitor Data Stack. The pointers for the various stacks have fixed locations in the BU-61580 address space.
OTHER RT FUNCTIONS
The BU-65170/61580 allows the hardwired RT Address to be read by the host processor. Also, there are options for the RT FLAG Status Word bit to be set under software control and/or automatically following a failure of the loopback self-test. Other software controllable RT options include software programmable RT Status and RT BIT words, automatic clearing of the Service Request Status Word bit following a Transmit Vector Word mode command, capabilities to clear and/or load the Time Tag Register following receipt of Synchronize mode commands, options regarding Data Word transfers for the Busy and/or Message Error (Illegal) Status Word bits, and for handling of 1553A and reserved mode codes.
MONITOR (MT) ARCHITECTURE
The BU-61580 provides three bus monitor (MT) modes: (1) The "AIM-HY" (default) or "AIM-HY'er" Word Monitor mode. (2) A Selective Message Monitor mode. (3) A Simultaneous Remote Terminal/Selective Message Monitor mode. Data Device Corporation www.ddc-web.com
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BU-65170/61580/61585 H1 web-09/02-0
Selective Message Monitor Memory Organization TABLE 30 illustrates a typical memory map for the ACE in the Selective Message Monitor mode. This mode of operation defines several fixed locations in the RAM. These locations allocate in a manner that is compatible with the combined RT/Selective Message Monitor mode. Refer to TABLE 30 for an example of a typical Selective Message Monitor Memory Map. The fixed memory map consists of two Monitor Command Stack Pointers (location 102h and 106h), two Monitor Data Stack Pointers (locations 103h and 107h), and a Selective Message Monitor Lookup Table (0280-02FFh) based on RT Address, T/R, and subaddress. Assume a Monitor Command Stack size of 1K words, and a Monitor Data Stack size of 2K words. Refer to FIGURE 8 for an illustration of the Selective Message Monitor operation. Upon receipt of a valid Command Word, the BU-61580 will reference the Selective Monitor Lookup Table (a fixed block of addresses) to check for the condition (disabled/enabled) of the current command. If disabled, the BU61580 will ignore (and not store) the current message; if enabled, the BU-61580 will create an entry in the Monitor Command Stack at the address location referenced by the Monitor Command Stack Pointer. Similar to RT mode, The ACE stores a Block Status Word, 16-bit Time Tag Word, and Data Block Pointer in the Message Descriptor, along with the received 1553 Command Word following reception of the Command Word. The ACE writes the Block Status and Time Tag Words at both the start and end of the message. The Monitor Block Status Word contains indications of message in-progress or message complete, bus channel, Monitor Data Stack Rollover, RT-to-RT transfer and RT-to-RT transfer errors, message format error, and other error conditions. TABLE 24 shows the Message Monitor Block Status Word. The Data Block Pointer references the first word stored in the Monitor Data Stack (the first word following the Command Word) for the current message. The BU-61580 will then proceed to store the
CONFIGURATION REGISTER #1 MONITOR COMMAND STACK POINTERS
TABLE 30. TYPICAL SELECTIVE MESSAGE MONITOR MEMORY MAP (SHOWN FOR 4K RAM) ADDRESS (HEX) 0000-0101 0102 0103 0104-0105 0106 0107 0108-027F 0280-02FF 0300-03FF 0400-07FF 0800-0FFF DESCRIPTION Not Used Monitor Command Stack Pointer A (fixed location) Monitor Data Stack Pointer A (fixed location) Not Used Monitor Command Stack Pointer B (fixed location) Monitor Data Stack Pointer B (fixed location) Not Used Selective Monitor Lookup Table (fixed area) Not Used Monitor Command Stack A Monitor Data Stack A
subsequent words from the message (possible second Command Word, Data Word(s), Status Word(s)) into consecutive locations in the Monitor Data Stack. The size of the Monitor Command Stack is programmable to 256, 1K, 4K, or 16K words. The Monitor Data Stack size is programmable to 512, 1K, 2K, 4K, 8K, 16K, 32K, or 64K words. Monitor interrupts may be enabled for Monitor Command Stack Rollover, Monitor Data Stack Rollover, and/or End-of-Message conditions. In addition, in the Word Monitor mode there may be an interrupt enabled for a Monitor Trigger condition.
PROCESSOR AND MEMORY INTERFACE
The ACE terminals provide much flexibility for interfacing to a host processor and optional external memory. FIGURE 1 shows that there are 14 control signals, 6 of which are dual purpose, for the processor/memory interface. FIGURES 9 through 14 illustrate six of the configurations that may be used for interfacing a
MONITOR DATA STACKS
MONITOR COMMAND STACKS
15
13
0
CURRENT AREA B/A BLOCK STATUS WORD TIME TAG WORD CURRENT COMMAND WORD DATA BLOCK POINTER RECEIVED COMMAND WORD MONITOR DATA BLOCK #N MONITOR DATA BLOCK #N + 1
NOTE
IF THIS BIT IS "0" (NOT SELECTED) NO WORDS ARE STORED IN EITHER THE COMMAND STACK OR DATA STACK. IN ADDITION, THE COMMAND AND DATA STACK POINTERS WILL NOT BE UPDATED.
MONITOR DATA STACK POINTERS
SELECTIVE MONITOR LOOKUP TABLES OFFSET BASED ON RTA4-RTA0, T/R, SA4 SELECTIVE MONITOR ENABLE (SEE NOTE)
FIGURE 8. SELECTIVE MESSAGE MONITOR MEMORY MANAGEMENT
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BU-65170 or BU-61580 to a host processor bus. The various possible configurations serve to reduce to an absolute minimum the amount of glue logic required to interface to 8-, 16-, and 32bit processor buses. Also included are features to facilitate interfacing to processors that do not have a "wait state" type of handshake acknowledgement. Finally, the ACE supports a reliable interface to an external dual port RAM. This type of interface minimizes the portion of the available processor bandwidth required to access the 1553 RAM. The 16-bit buffered mode (FIGURE 9) is the most common configuration used. It provides a direct, shared RAM interface to a 16-bit or 32-bit microprocessor. In this mode, the ACE's internal address and data buffers provide the necessary isolation between the host processor's address and data buses and the corresponding internal memory buses. In the buffered mode, the 1553 shared RAM address space limit is the BU-65170/61580's 4K words of internal RAM. The 16-bit buffered mode provides a pair of pin-programmable options: (1) The logic sense of the RD/WR control input is selectable by the POLARITY_SEL input: For example, write when RD/WR is low for Motorola 680X0 processors; write when RD/WR is high for the Intel i960 series microprocessors. (2) By strapping the input signal ZERO_WAIT to logic "1," the ACE terminals may interface to processors that have an acknowledge type of handshake input to accommodate hardware controlled wait states; most current processor chips have such an input. In this case, the BU-65170/61580 will assert its READYD output low only after it has latched WRITE data internally or has presented READ data on D15D0. By strapping ZERO_WAIT to logic "0," it is possible to easily interface the BU-65170/61580 to processors that do not have an acknowledge type of handshake input. An example of such a processor is Analog Device's ADSP2101 DSP chip. In this configuration, the processor can clear its strobe output before the completion of access to the BU-65170/61580 internal RAM or register. In this case, READYD will go high following the rising edge of STRBD and will stay high until completion of the transfer. READYD will normally be low when ZERO_WAIT is low. Similar to the 16-bit buffered mode, the 16-bit transparent mode (FIGURE 10) supports a shared RAM interface to a host CPU. The transparent mode offers the advantage of allowing the buffer RAM size to be expanded to up to 64K words, using external RAM. A disadvantage of the transparent mode is that it requires external address and data buffers to isolate the processor buses from the memory/BU-65170/61580 buses. A modified version of the transparent mode involves the use of dual port RAM, rather than conventional static RAM. Refer to FIGURE 11. This allows the host to access RAM very quickly, the only limitation being the access time of the dual port RAM. This configuration eliminates the BU-65170/61580 arbitration delays for memory accesses. The worst case delay time occurs only during a simultaneous access by the host and the BU65170/61580 1553 logic to the same memory address. In general, this will occur very rarely and the ACE limits the delay to approximately 250 ns.
FIGURE 12 illustrates the connections for the 16-bit Direct Memory Access (DMA) mode. In this configuration the host processor, rather than the ACE terminal, arbitrates the use of the address and data buses. The arbitration involves the two DMA output signals Request (DTREQ) and Acknowledge (DTACK), and the input signal Grant (DTGRT). The DMA interface allows the ACE components to interface to large amounts of system RAM while eliminating the need for external buffers. For system address spaces larger than 64K words, it is necessary for the host processor to provide a page register for the upper address bits (above A15) when the BU-65170/61580 accesses the RAM (while asserting DTACK low). The internal RAM is accessible through the standard ACE interface (SELECT, STRBD, READYD, etc). The host CPU may access external RAM by the ACE's arbitration logic and output control signals, as illustrated in FIGURE 12. Alternatively, control of the RAM may be shared by both the host processor and the ACE, as illustrated in FIGURE 13. The latter requires the use of external logic, but allows the processor to access the RAM directly at the full access speed of the RAM, rather than waiting for the ACE handshake acknowledge output (READYD). FIGURE 14 illustrates the 8-bit buffered mode. This interface allows a direct connection to 8-bit microprocessors and 8-bit microcontrollers. As in the 16-bit buffered configuration, the buffer RAM limit is the BU-65170/61580's 4K words of internal RAM. In the 8-bit mode, the host CPU accesses the BU65170/61580's internal registers and RAM by a pair of 8-bit registers embedded in the ACE interface. The 8-bit interface may be further configured by three strappable inputs: ZERO_WAIT, POLARITY_SEL, and TRIGGER_SEL. By connecting ZERO_WAIT to logic "0," the BU-65170/61580 may be interfaced with minimal "glue" logic to 8-bit microcontrollers, such as the Intel 8051 series, that do not have an Acknowledge type of handshake input. The programmable inputs POLARITY_SEL and TRIGGER_SEL allow the BU-65170/61580 to accommodate the different byte ordering conventions and "A0" logic sense utilized by different 8-bit processor families.
PROCESSOR INTERFACE TIMING
FIGURES 15 and 16 illustrate the timing for the host processor to access the ACE's internal RAM or registers in the 16-bit, buffered, non-zero, wait-mode. FIGURE 15 illustrates the 16-bit buffered, nonzero wait mode read cycle timing while FIGURE 16 shows the 16-bit, buffered, nonzero wait mode write cycle timing. During a CPU transfer cycle, the signals STRBD and SELECT must be sampled low on the rising edge of the system clock to request access to the BU-65170/61580's internal shared RAM. The transfer will begin on the first rising system clock edge when (SELECT and STRBD) is low and the 1553 protocol/memory management unit is not accessing the internal RAM. The falling edge of the output signal IOEN indicates the start of the transfer. The ACE latches the signals MEM/REG and RD/WR internally on the first falling clock edge after the start of the transfer cycle. The address inputs latch internally on the first rising clock edge after the signal IOEN goes low. Note that the address lines may be latched at any time using the ADDR_LAT input signal. The output signal READYD will be asserted low on the third rising system clock edge after IOEN goes low. The assertion of BU-65170/61580/61585 H1 web-09/02-0
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READYD low indicates to the host processor that read data is available on the parallel data bus, or that write data has been stored. At this time, the CPU should bring the signal STRBD high, completing the transfer cycle. Address Latch Timing FIGURE 17 illustrates the operation and timing of the address input latches for the buffered interface mode. In the transparent mode, the address buffers are always transparent. Since the transparent mode requires the use of external buffers, external address latches would be required to demultiplex a multiplexed address bus. In the buffered mode, however, the ACE's internal address latches may be used to perform the demultiplexing function. The ADDR_LAT input signal controls address latch operation. When ADDR_LAT is high, the outputs of the latch (which drive the ACE's internal memory bus) track the state of address inputs A15 - A00. When it is low, the internal memory bus remains latched at the state of A15 - A00 just prior to the falling edge of ADDR_LAT.
Note that the timeout value of the watchdog timer depends on the mode of operation selected (1553A or 1553B). A failure of the loop test results in setting a bit in the message's Block Status Word and, if enabled, will result in an interrupt request. With appropriate host processor software, the BC off-line test is able to exercise the parallel and serial data paths, encoder, decoder, and a substantial portion of the BC protocol and memory management logic. There are additional built-in self-test features, that involve the use of three configuration register bits and the eight test registers. This allows a test of approximately 99% of the J' chip's internal logic. These tests include an encoder test, a decoder test, a register test, a protocol test, and a test of the fail-safe (transmitter timeout) timer. There is also a test mode. In the test mode, the host processor can emulate arbitrary activity on the 1553 buses by writing to a pair of test registers. The test mode can be operated in conjunction with the Word Monitor mode to facilitate end-to-end selftests.
RAM PARITY GENERATION AND CHECKING
MISCELLANEOUS
SELF-TEST
The BU-65170/61580 products incorporate several self-test features. These features include an on-line wraparound self-test for all messages in BC and RT modes, an off-line wraparound selftest for BC mode, and several other internal self-test features. The BC/RT on-line loop test involves a wraparound test of the encoder/decoder and transceiver. The BC off-line self-test involves the encoder/decoder, but not the transceiver. These tests entail checking the received version of every transmitted word for validity (sync, encoding, bit count, parity) and checking the received version of the last transmitted word for a bit-by-bit comparison with the encoded word. The loopback test also fails if there is a timeout of the internal transmitter watchdog timer.
The architecture of the J' monolithic is such that the amount of buffered RAM may be extended beyond the 4K words of on-chip J' RAM. For this off-chip buffered RAM, the J' chip includes provisions to implement parity generation and checking. Parity generation and checking provides a mechanism for checking the data integrity of the internal, buffered memory. Furthermore, 17bit, rather than 16-bit, wide buffered RAM would be used. For this RAM, the J' chip will generate the 17th bit (parity bit) for all (host and 1553) write accesses and check the parity bit for all read accesses. If a parity error occurs, an interrupt request may be issued, and the corresponding bit in the Interrupt Status Register would be set. The BU-61585 incorporates an additional 8K x 17 RAM chip.
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BU-65170/61580/61585 H1 web-09/02-0
+15V 16 MHz CLOCK OSCILLATOR CLK IN
+5V
D15-D0 TX/RXA 1 N/C A15-A12 2 3 A11-A0 TX/RXA 4 8 7 5
55
CH. A
55 CPU ADDRESS LATCH (NOTE 1) ADDR_LAT
TRANSPARENT/BUFFERED +5V 16/8_BIT +5V TRIGGER_SEL N/C N/C
(NOTE 2)
55 TX/RXB 1 2 3 8 7 5 4 55 CH. B
MSB/LSB POLARITY_SEL
HOST
(NOTE 3)
ZERO_WAIT
ACE
TX/RXB
SELECT ADDRESS DECODER MEM/REG
RD/WR CPU STROBE CPU ACKNOWLEDGE
(NOTE 4)
RD/WR STRBD READYD TAG_CLK +5V RTAD4-RTAD0 RTADP RT ADDRESS, PARITY
RESET
MSTCLR
SSFLAG/EXT_TRIG
CPU INTERRUPT REQUEST
INT
NOTES:
1. CPU ADDRESS LATCH SIGNAL PROVIDED BY PROCESSORS WITH MULTIPLEXED ADDRESS/DATA BUSES. 2. IF POLARITY_SEL = "1", RD/WR IS HIGH TO READ, LOW TO WRITE. IF POLARITY_SEL = "0", RD/WR IS LOW TO READ, HIGH TO WRITE. 3. ZERO_WAIT SHOULD BE STRAPPED TO LOGIC "1" FOR NON-ZERO WAIT INTERFACE AND TO LOGIC "0" FOR ZERO WAIT INTERFACE. 4. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY FOR NON-ZERO WAIT TYPE OF INTERFACE.
* Additional address lines A12 and A13 are required with the BU-61585.
FIGURE 9. 16-BIT BUFFERED MODE
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+15V 16 MHz CLOCK OSCILLATOR CLK IN
+5V
CPU D15-D0
'245 DIR EN
D15-D0 55 TX/RXA 1 WR RAM 64K x 16 MAX OE CS TX/RXA IOEN DTREQ DTGRT MEMWR MEMOE 2 3 4 55 8 7 5 CH. A
EN CPU A15-A0 '244 ADDRESS DECODER EN A15-A0 55 TX/RXB 1 MEMENA-IN 2 3 8 7 5 4 55 CH. B
HOST
MEMENA-OUT TRANSPARENT/BUFFERED
ACE
TX/RXB
SELECT ADDRESS DECODER MEM/REG
RD/WR CPU STROBE CPU ACKNOWLEDGE STRBD READYD TAG_CLK +5V RESET MSTCLR RTAD4-RTAD0 RTADP RT ADDRESS, PARITY
SSFLAG/EXT_TRIG
CPU INTERRUPT REQUEST
INT
FIGURE 10. 16-BIT TRANSPARENT MODE
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CS-L
CS-R
MEMENA-OUT
WR-L DUAL PORT RAM
WR-R
MEMWR
OE-L BUSY-L
OE-R BUSY-R
MEMOE
N/C D15-D0
CPU D15-D0
CPU ADDRESS
A15-A0
RD/WR +5V DIR
RD/WR
MEMENA-IN MEM/REG
HOST
1553 RAM SELECT ADDRESS DECODER 1553 REG SELECT CPU A4-A0
'245 EN
ACE
IOEN
EN A4-A0 '244 N/C
DTREQ DTGRT
DTACK SELECT
CPU DATA STROBE +5V
STRBD
TRANSPARENT/BUFFERED CPU READY READYD +5V RESET MSTCLR
CPU INTERRUPT REQUEST
INT
FIGURE 11. 16-BIT TRANSPARENT MODE USING DUAL PORT RAM
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+15V 16 MHz CLOCK OSCILLATOR CLK IN
+5V
CPU D15-D0 RD/WR
D15-D0 TX/RXA RD/WR 1 2 WR RAM 64K x 16 MAX OE CS DTREQ DTGRT DTACK MEMWR MEMOE TX/RXA 3 4 8 7 5
55
CH. A
55
CPU A15-A0
A15-A0
55 TX/RXB 1 2 3 8 7 5 CH. B
HOST
ADDRESS DECODER EN
MEMENA-IN
ACE
TX/RXB
4 55
MEMENA-OUT
SELECT ADDRESS DECODER +5V TRANSPARENT/BUFFERED MEM/REG
CPU STROBE CPU ACKNOWLEDGE
STRBD RTAD4-RTAD0 READYD TAG_CLK +5V RTADP RT ADDRESS, PARITY
RESET
MSTCLR SSFLAG/EXT_TRIG
CPU INTERRUPT REQUEST
INT
FIGURE 12. 16-BIT DIRECT MEMORY ACCESS (DMA) MODE
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25
+15V 16 MHz CLOCK OSCILLATOR CPU D15-D0 RD/WR CLK IN
+5V
D15-D0 RD/WR 55 TX/RXA MEMWR WR RAM 64K x 16 MAX OE CS MEMOE TX/RXA 1 2 3 4 55 8 7 5 CH. A
DTREQ DTGRT DTACK 55 TX/RXB 1 CPU A15-A0 +5V A15-A0 2 3 MEMENA-IN MEMENA-OUT MEM/REG 1553 RAM SELECT ADDRESS DECODER 1553 REG SELECT +5V TRANSPARENT/BUFFERED SELECT 8 7 5 4 55 CH. B
HOST
ACE
TX/RXB
CPU STROBE CPU ACKNOWLEDGE
STRBD RTAD4-RTAD0 READYD TAG_CLK +5V RTADP RT ADDRESS, PARITY
RESET
MSTCLR SSFLAG/EXT_TRIG
CPU INTERRUPT REQUEST
INT
FIGURE 13. 16-BIT DMA MODE WITH EXTERNAL LOGIC TO REDUCE PROCESSOR ACCESS TIME TO EXTERNAL RAM
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16 MHz CLOCK OSCILLATOR CPU D7-D0
(NOTE 1)
+15V CLK IN
+5V
D15-D8
D7-D0 TX/RXA N/C A15-A12 1 2 CPU A12-A0 A12-A1 CPU ADDRESS LATCH (NOTE 2) CPU A0 A11-A0 ADDR_LAT MSB/LSB 16/8_BIT TRANSPARENT/BUFFERED +5V 3 TX/RXA 4 8 7 5
55
CH. A
55
(NOTE 3)
POLARITY_SEL
55 TX/RXB 1 8 7 5 3 4 55 CH. B
(NOTE 4)
ZERO_WAIT
2
HOST
(NOTE 5)
TRIGGER_SEL
ACE
TX/RXB
SELECT ADDRESS DECODER MEM/REG
RD/WR CPU STROBE CPU ACKNOWLEDGE
(NOTE 6)
RD/WR STRBD READYD TAG_CLK +5V RTAD4-RTAD0 RTADP RT ADDRESS, PARITY
RESET
MSTCLR
SSFLAG/EXT_TRIG
CPU INTERRUPT REQUEST
INT
NOTES:
1. CPU D7-D0 CONNECTS TO BOTH D15-D8 AND D7-D0. 2. CPU ADDRESS LATCH SIGNAL PROVIDED BY PROCESSORS WITH MULTIPLEXED ADDRESS/DATA BUFFERS. 3. IF POLARITY_SEL = "1", THEN MSB/LSB SELECTS THE MOST SIGNIFICANT BYTE WHEN LOW, AND THE LEAST SIGNIFICANT BYTE WHEN HIGH. IF POLARITY_SEL = "0", THEN MSB/LSB SELECTS THE LEAST SIGNIFICANT BYTE WHEN LOW, AND THE MOST SIGNIFICANT BYTE WHEN HIGH. 4. ZERO WAIT SHOULD BE STRAPPED TO LOGIC "1" FOR NON-ZERO WAIT INTERFACE AND TO LOGIC "0" FOR ZERO WAIT INTERFACE. 5. OPERATION OF TRIGGER_SELECT INPUT IS AS FOLLOWS: FOR NON-ZERO WAIT INTERFACE (ZERO WAIT = "1"): IF TRIGGER_SEL = "1", THEN INTERNAL 16-BIT TRANSFERS ARE TRIGGERED BY THE MOST SIGNIFICANT BYTE TRANSFER READ ACCESSES AND BY THE LEAST SIGNIFICANT BYTE TRANSFER FOR WRITE ACCESSES. IF TRIGGER_SEL = "0", THEN INTERNAL 16-BIT TRANSFERS ARE TRIGGERED BY THE LEAST SIGNIFICANT BYTE TRANSFER FOR READ ACESSES AND BY THE MOST SIGNIFICANT BYTE TRANSFER FOR WRITE ACCESSES. FOR ZERO WAIT INTERFACE (ZERO WAIT = "0"): IF TRIGGER_SEL = "1", THEN INTERNAL 16-BIT TRANSFERS ARE TRIGGERED BY THE LEAST SIGNIFICANT BYTE TRANSFER, FOR BOTH READ AND WRITE ACCESSES. IF TRIGGER_SEL = "0", THEN INTERNAL 16-BIT TRANSFERS ARE TRIGGERED BY THE MOST SIGNIFICANT BYTE TRANSFER, FOR BOTH READ AND WRITE ACCESSES. 6. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY FOR NON-ZERO WAIT TYPE OF INTERFACE.
* Additional address lines A12 and A13 are required with the BU-61585.
FIGURE 14. 8-BIT BUFFERED MODE
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t5
CLOCK IN
t1
SELECT
(Note 2,7) t2 t6 t14 t18
STRBD
(Note 2)
MEM/REG
(Note 3,4,7) t3 t7
VALID
t8
RD/WR
(Note 4,5)
IOEN
(Note 2,6)
READYD
(Note 6)
;; ;; ; ;; ;; ;; ;; ;; ;
t10 t19
A15-A0
(Note 7,8,9)
D15-D0
(Note 6)
FIGURE 15. CPU READING RAM (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)
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;; ;; ;; ;; ;; ;;
t11 t13 t15 t4 t9 t12
VALID VALID
;
t17
t16
; ;
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TABLE FOR FIGURE 15. CPU READING RAM OR REGISTERS (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE) REF t1 t2 t2 t2 t2 t3 t3 t4 t4 t5 t6 t7 t8 t9 t10 t11 t11 t11 t11 t12 t12 t13 t14 t15 t16 t17 t18 t19 DESCRIPTION SELECT and STRBD low setup time prior to clock rising edge SELECT and STRBD low delay to IOEN low (uncontended access @ 16 MHz) SELECT and STRBD low delay to IOEN low (contended access @ 16 MHz) SELECT and STRBD low delay to IOEN low (uncontended access @ 12 MHz) SELECT and STRBD low delay to IOEN low (contended access @ 12 MHz) MEM/REG, RD/WR setup time following SELECT and STRBD low(@ 16 MHz) MEM/REG, RD/WR setup time following SELECT and STRBD low(@ 12 MHz) Address valid setup time following SELECT and STRBD low (@ 16 MHz) Address valid setup time following SELECT and STRBD low (@ 12 MHz) CLOCK IN rising edge delay to IOEN falling edge SELECT hold time following IOEN falling MEM/REG, RD/WR setup time prior to CLOCK IN falling edge MEM/REG, RD/WR hold time prior to CLOCK IN falling edge Address valid setup time prior to CLOCK IN rising edge Address hold time following CLOCK IN rising edge IOEN falling delay to READYD falling (reading RAM @ 16 MHz) IOEN falling delay to READYD falling (reading RAM @ 12 MHz) IOEN falling delay to READYD falling (reading registers @ 16 MHz) IOEN falling delay to READYD falling (reading registers @ 12 MHz) Output Data valid prior to READYD falling (@ 16 MHz) Output Data valid prior to READYD falling (@ 12 MHz) CLOCK IN rising edge delay to READYD falling READYD falling to STRBD rising release time STRBD rising edge delay to IOEN rising edge and READYD rising edge Output Data hold time following STRBD rising edge STRBD rising delay to output Data tri-state STRBD high hold time from READYD rising CLOCK IN rising edge delay to Output Data valid 0 60 0 40 0 10 30 30 30 170 235 170 235 33 54 35 30 187.5 250 187.5 250 205 265 205 265 MIN 10 107.5 2.8 128.3 3.7 10 20 30 50 35 TYP MAX UNITS ns ns s ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note 6 note 6 note 6 note 2 notes 3, 4, 5, 7 notes 3, 4, 5, 7 notes 7, 8, 9 notes 7, 8, 9, 10 notes 6, 10 notes 6, 10 notes 6, 10 notes 6, 10 note 6 note 6 note 6
NOTE REFERENCE
notes 2, 10 notes 2, 6 notes 2, 6 notes 2, 6 notes 2, 6 notes 3, 4, 5, 7 notes 3, 4, 5, 7
Notes for FIGURE 15 and associated table. 1. For the 16-bit buffered nonzero wait configuration, TRANSPARENT/BUFFERED must be connected to logic "0". ZERO_WAIT and DTREQ/16/8 must be connected to logic "1". The inputs TRIGGER_SEL and MSB/LSB may be connected to either +5 V or ground. 2. SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT* STRBD is sampled low (satisfying t1) and the BU-65170/61580's protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low, starting the transfer cycle. After IOEN goes low, SELECT may be released high. 3. MEM/REG must be presented high for memory access, low for register access. 4. MEM/REG and RD/WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM/REG and RD/WR become latched internally. 5. The logic sense for RD/WR in the diagram assumes that POLARITY_SEL is connected to logic "1." If POLARITY_SEL is connected to logic "0," RD/WR must be asserted low to read.
6. The timing for IOEN, READYD and D15-D0 assumes a 50 pf load. For loading above 50 pf, the validity of IOEN, READYD, and D15-D0 is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max. 7. Timing for A15-A0, MEM/REG and SELECT assumes ADDR-LAT is connected to logic "1." Refer to Address Latch timing for additional details. 8. Internal RAM is accessed by A11 through A0 (A13 through A0 for 61585 and 61586). Registers are accessed by A4 through A0. 9. The address bus A15-A0 is internally buffered transparently until the first rising edge of CLK after IOEN goes low. After this CLK edge, A15-A0 become latched internally. 10. Setup time given for use in worst case timing calculations. None of the ACE input signals are required to be synchronized to the system clock. For ACE applications only, where SELECT and STRBD do not meet the setup time of t1, but occur during the setup window of an internal flip-flop, an additional clock cycle will be inserted between the falling clock edge that latches MEM/REG and RD/WR and the rising clock edge that latches the Address (A15A0). When this occurs, the pulse width of IOEN falling to READYD falling (t11) increases by one clock cycle and the address hold time (t10) must be increased be one clock cycle.
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t6
CLOCK IN
t1
SELECT
(Note 2,7) t2
t7
t16
t18
STRBD
(Note 2)
MEM/REG
(Note 3,4,7) t3 t8
VALID
t9
RD/WR
(Note 4,5)
IOEN
(Note 2,6)
t14 t15 t4 t17
READYD
(Note 6)
t10 t12
VALID
(Note 7,8,9,10)
A15-A0
t5
t11
VALID
(Note 9,10)
D15-D0
t13
FIGURE 16. CPU WRITING RAM (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)
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TABLE FOR FIGURE 16. CPU WRITING RAM OR REGISTERS (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE) REF t1 t2 t2 t2 t2 t3 t3 t4 t4 t5 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t14 t15 t16 t17 t18 DESCRIPTION SELECT and STRBD low setup time prior to CLOCK IN rising edge SELECT and STRBD low delay to IOEN low (uncontended access @ 16 MHz) SELECT and STRBD low delay to IOEN low (contended access @ 16 MHz) SELECT and STRBD low delay to IOEN low (uncontended access @ 12 MHz) SELECT and STRBD low delay to IOEN low (contended access @ 12 MHz) MEM/REG, RD/WR setup time following SELECT and STRBD low(@ 16 MHz) MEM/REG, RD/WR setup time following SELECT and STRBD low(@ 12 MHz) Address valid setup time following SELECT and STRBD low (@ 16 MHz) Address valid setup time following SELECT and STRBD low (@ 12 MHz) Input Data valid setup time following SELECT and STRBD low (@ 16 MHz) Input Data valid setup time following SELECT and STRBD low (@ 12 MHz) CLOCK IN rising edge delay to IOEN falling edge SELECT hold time following IOEN falling MEM/REG, RD/WR setup time prior to CLOCK IN falling edge MEM/REG, RD/WR hold time prior to CLOCK IN falling edge Address valid setup time prior to CLOCK IN rising edge Input Data valid setup time prior to CLOCK IN rising edge Address valid hold time following to CLOCK IN rising edge Input Data valid hold time following CLOCK IN rising edge IOEN falling delay to READYD falling (@ 16 MHz) IOEN falling delay to READYD falling (@ 16 MHz) CLOCK IN rising edge delay to READYD falling READYD falling to STRBD rising edge release time STRBD rising edge delay to IOEN rising edge and READYD rising edge STRBD valid high hold time from READYD rising edge 0 0 10 30 30 10 30 30 170 235 187.5 250 205 265 35 30 MIN 10 107.5 2.8 128.3 3.7 10 20 30 50 50 70 35 TYP MAX UNITS ns ns s ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note 6 notes 7, 8, 9, 10 notes 9, 10 notes 6, 10 notes 6, 10 note 6 note 6 note 2 notes 3, 4, 5, 7 notes 3, 4, 5, 7 notes 7, 8, 9 NOTE REFERENCE notes 2, 10 notes 2, 6 notes 2, 6 notes 2, 6 notes 2, 6 notes 3, 4, 5, 7 notes 3, 4, 5, 7
Notes for FIGURE 16 and associated table. 1. For the 16-bit buffered nonzero wait configuration, TRANSPARENT/BUFFERED must be connected to logic "0". ZERO_WAIT and DTREQ/16/8 must be connected to logic "1". The inputs TRIGGER_SEL and MSB/LSB may be connected to either +5 V or ground. 2. SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT*STRBD is sampled low (satisfying t1) and the BU-65170/61580's protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low, starting the transfer cycle. After IOEN goes low, SELECT may be released high. 3. MEM/REG must be presented high for memory access, low for register access. 4. MEM/REG and RD/WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM/REG and RD/WR become latched internally. 5. The logic sense for RD/WR in the diagram assumes that POLARITY_SEL is connected to logic "1." If POLARITY_SEL is connected to logic "0," RD/WR must be asserted high to write.
6. The timing for IOEN, READYD and D15-D0 assumes a 50 pf load. For loading above 50 pf, the validity of IOEN, READYD, and D15-D0 is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max. 7. Timing for A15-A0, MEM/REG and SELECT assumes ADDR-LAT is connected to logic "1." Refer to Address Latch timing for additional details. 8. Internal RAM is accessed by A11 through A0 (A13 through A0 for 61585 and 61586). Registers are accessed by A4 through A0. 9. The address bus A15-A0 is internally buffered transparently until the first rising edge of CLK after IOEN goes low. After this CLK edge, A15-A0 become latched internally. 10. Setup time given for use in worst case timing calculations. None of the ACE input signals are required to be synchronized to the system clock. For ACE applications only, where SELECT and STRBD do not meet the setup time of t1, but occur during the setup window of an internal flip-flop, an additional clock cycle will be inserted between the falling clock edge that latches MEM/REG and RD/WR and the rising clock edge that latches the Address (A15-A0) and data (D15-D0). When this occurs, the pulse width of IOEN falling to READYD falling (t14) increases by one clock cycle and the address hold time (t12 + t13) must be increased be one clock cycle.
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SELECT MSB/LSB INPUT SIGNALS MEM/REG A15-A0 (1) (2) (3) t4 t5 ADDR_LAT t2 SELECT MSB/LSB INTERNAL VALUES MEM/REG A15-A0 (1) (2) (3) (4) t3 t1 (4) (5)
FIGURE 17. ADDRESS LATCH TIMING
Notes for FIGURE 17 and associated table. 1. Applicable to buffered mode only. Address SELECT AND MEM/REG latches are always transparent in the transparent mode of operation. 2. Latches are transparent when ADDR_LAT is high. Internal values do not update when ADDR_LAT is low. 3. MSB/LSB input signal is applicable to 8-bit mode only (16/8 input = logic "0"). MSB/LSB input is a "don't care" for 16-bit operation.
TABLE FOR FIGURE 17. ADDRESS LATCH TIMING REF t1 t2 t3 t4 t5 ADDR_LAT pulse width ADDR_LAT high delay to internal signals valid Propagation delay from external input signals to internal signals valid Input setup time prior to falling edge of ADDR_LAT Input hold time following falling edge of ADDR_LAT 10 20 DESCRIPTION MIN 20 10 10 TYP MAX UNITS ns ns ns ns ns
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INTERFACE TO MIL-STD-1553 BUS
FIGURE 18 illustrates the interface from the various versions of the ACE series terminals to a 1553 bus. The figure also indicates connections for both direct (short stub) and transformer (long stub) coupling, plus the peak-to-peak voltage levels that appear at various points (when transmitting). TABLE 31 lists the characteristics of the required isolation transformers for the various ACE terminals, the DDC and Beta Transformer Technology Corporation corresponding part number, and the MIL (DESC) drawing number (if applicable). Beta Transformer Technology is a direct subsidiary of DDC. For both coupling configurations, the isolation transformer is the transformer that interfaces directly to the ACE component. For the transformer (long stub) coupling configuration, the transformer that interfaces the stub to the bus is the coupling transformer. The turns ratio of the isolation transformer varies, depending upon the peak-to-peak output voltage of the specific ACE terminal. The transmitter voltage of each model of the BU-65170/61580 varies directly as a function of the power supply voltage. The turns ratios of the respective transformers will yield a secondary voltage of approximately 28 volts peak-to-peak on the outer taps (used for direct coupling) and 20 volts peak-to-peak on the inner taps (used for stub coupling). In accordance with MIL-STD-1553B, the turns ratio of the coupling transformer is 1.0 to 1.4. Both coupling configurations require an isolation resistor to be in series with each leg connecting to the 1553 bus; this protects the bus against short circuit conditions in the transformers, stubs, or terminal components.
TABLE 31. ISOLATION TRANSFORMER GUIDE TURNS RATIO ACE PART NUMBER BU-65170X1 BU-65171X1 BU-61580X1 BU-61581X1 BU-61585X1 BU-61586X1 DIRECT XFORMER COUPLED COUPLED 1.41:1 2:1 RECOMMENDED XFORMER PLUG-IN BUS-25679, B-2203, M21038/27 -03 SURFACE MOUNT B-2387 M21038/27 -12, M21038/27 -17 LPB-5002 LPB-5009 LPB-6002 LPB-6009 LPB-5001 LPB-5008 LPB-6001 LPB-6008 B-2388 M21038/27 -13, B-2334, M21038/27 -18
BU-65170X2 BU-65171X2 BU-61580X2 BU-61581X2 BU-61585X2 BU-61586X2
1.20:1
1:0.6
BUS-29854
1.25:1 (Note 5)
B-2204, M21038/27 -03
BU-65170X3 BU-65171X3 BU-61580X3 BU-61581X3 BU-61585X3 BU-61586X3 BU-65170X6 BU-65171X6 BU-61580X6 BU-61581X6 BU-61585X6 BU-61586X6
1:2.5
1:1.79
See Table 32
Notes for TABLE 31 and FIGURE 18: (1) Shown for one of two redundant buses that interface to the BU-65170 or BU61580. (2) Transmitted voltage level on 1553 bus is 6 Vp-p min, 7 Vp-p nominal, 9 Vp-p max. (3) Required tolerance on isolation resistors is 2%. Instantaneous power dissipation (when transmitting) is approximately 0.5 W (typ), 0.8 W (max). (4) Transformer pin numbering is correct for the DDC (e.g., BUS-25679) transformers. For the Beta transformers (e.g., B-2203) or the QPL-21038-31 transformers (e.g., M21038/27-02), the winding sense and turns ratio are mechanically the same, but with reversed pin numbering; therefore, it is necessary to reverse pins 8 and 4 or pins 7 and 5 for the Beta or QPL transformers (Note: DDC transformer part numbers begin with a BUS- prefix, while Beta transformer part numbers begin with a B- prefix). (5)The B-2204, B-2388, and B-2344 transformers have a slightly different turns ratio on the direct coupled taps then the turns ratio of the BUS-29854 direct coupled taps. They do, however, have the same transformer coupled ratio. For transformer coupled applications, either transformer may be used. The transceiver in the BU-65170X2 and the BU-61580X2 was designed to work with a 1:0.83 ratio for direct coupled applications. For direct coupled applications, the 1.20:1 turns ration is recommended, but the 1.25:1 may be used. The 1.25:1 turns ratio will result in a slightly lower transmitter amplitude. (Approximately 3.6% lower) and a slight shift in the ACE's receiver threshold.
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TRANSFORMERS
In selecting isolation transformers to be used with the X3, X6 ACE, there is a limitation on the maximum amount of leakage inductance. If this limit is exceeded, the transmitter rise and fall times may increase, possibly causing the bus amplitude to fall below the minimum level required by MIL-STD-1553. In addition, an excessive leakage imbalance may result in a transformer dynamic offset that exceeds 1553 specifications. The maximum allowable leakage inductance is 6.0 H, and is measured as follows: The side of the transformer that connects to the ACE is defined as the "primary" winding. If one side of the primary is shorted to the primary center-tap, the inductance should be measured across the "secondary" (stub side) winding. This inductance
must be less than 6.0 H. Similarly, if the other side of the primary is shorted to the primary center-tap, the inductance measured across the "secondary" (stub side) winding must also be less than 6.0 H. The difference between these two measurements is the "differential" leakage inductance. This value must be less than 1.0 H. Beta Transformer Technology Corporation (BTTC), a subsidiary of DDC, manufactures transformers in a variety of mechanical configurations with the required turns ratios of 1:2.5 direct coupled, and 1:1.79 transformer coupled. TABLE 32 provides a listing of many of these transformers.For further information, contact BTTC at 631-244-7393 or at www.bttc-beta.com.
TABLE 32. BTTC TRANSFORMERS FOR USE WITH X3, X6 ACE
TRANSFORMER CONFIGURATION Single epoxy transformer, through-hole, 0.625" X 0.625", 0.250" max height Single epoxy transformer, through-hole, 0.625" X 0.625", 0.220" max height. May be used with BU-6XXXXX4 versions of the Enhanced Mini-ACE. Single epoxy transformer, flat pack, 0.625" X 0.625", 0.275" max height Single epoxy transformer, surface mount, 0.625" X 0.625", 0.275" max height Single epoxy transformer, surface mount, hi-temp solder, 0.625" X 0.625", 0.220" max height. May be used with BU-6XXXXX4 versions of the Enhanced Mini-ACE.B-3819 Single epoxy transformer, flat pack, 0.625" X 0.625", 0.150" max height Single epoxy transformer, surface mount, 0.625" X 0.625", 0.150" max height Single epoxy transformer, through hole, transformer coupled only, 0.500" X 0.350", 0.250" max height Dual epoxy transformer, twin stacked, 0.625" X 0.625", 0.280" max height Dual epoxy transformer, twin stacked, surface mount, 0.625" X 0.625", 0.280" max height Dual epoxy transformer, twin stacked, flat pack, 0.625" X 0.625", 0.280" max height Dual epoxy transformer, side by side, through-hole, 0.930" X 0.630", 0.155" max height Dual epoxy transformer, side by side, flat pack, 0.930" X 0.630", 0.155" max height Dual epoxy transformer, side by side, surface mount, 0.930" X 0.630", 0.155" max height Dual epoxy transformer, side by side, surface mount, 1.410" X 0.750", 0.130" max height Single metal transformer, hermetically sealed, flat pack, 0.630" X 0.630", 0.175" max height Single metal transformer, hermetically sealed, surface mount, 0.630" X 0.630", 0.175" max height NOT RECOMMENDED
Notes: 1. For the BU-6XXXXX3/6 versions of the ACE with -1553B transceivers, any of the transformers listed in the table may be used. 2. DLP-7115 operates to +105C max. All other transformers listed operate to +130C max.
BTTC PART NO. B-3067 B-3226 B-3818 B-3231 B-3227 B-3819 LPB-5014 LPB-5015 B-3229 TST-9007 TST-9017 TST-9027 B-3300 B-3261 B-3310 DLP-7115 (see note 2) HLP-6014 HLP-6015 DLP-7014 SLP-8007 SLP-8024
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DIRECT COUPLED (SHORT STUB) 1.4:1
Z0 (70 to 85)
1 2 3
8 4
55 1 FT MAX 55
BU-61580X1
39 VPP
28 VPP ISOLATION TRANSFORMER
OR
TRANSFORMER COUPLED (LONG STUB) 2:1 1:1.4
1 2 3
39 VPP
7 5
20 FT MAX
8 4
1 3
0.75 Z0 28 VPP 0.75 Z0
ISOLATION TRANSFORMER
20 VPP
COUPLING TRANSFORMER
DIRECT COUPLED (SHORT STUB) 1:0.83
1 2 3
8 4
55 1 FT MAX 55
BU-61580X2
33 VPP
ISOLATION 28 VPP TRANSFORMER
OR
TRANSFORMER COUPLED (LONG STUB) 1:0.6 1:1.4
1 2 3
33 VPP
7 5
20 FT MAX
8 4
1 3
0.75 Z0 28 VPP 0.75 Z0
ISOLATION TRANSFORMER
20 VPP
COUPLING TRANSFORMER
DIRECT COUPLED (SHORT STUB)
1:2.5 1 2 3 4 55 11.6 VPP
ISOLATION 28 VPP TRANSFORMER
8
55 1 FT MAX
BU-61580X3 BU-61580X6
OR
TRANSFORMER COUPLED (LONG STUB)
1:1.79 1 2 3 11.6 VPP 5 20 VPP 4 7 20 FT MAX 8
1:1.4
1 3
0.75 Z0 28 VPP 0.75 Z0
ISOLATION TRANSFORMER
COUPLING TRANSFORMER
Z0 (70 to 85)
Note: The BU-65170XX, BU-65171XX, BU-61581XX, BU-61585XX and BU-61586XX models are interfaced the same as the corresponding BU-61580XX model is shown (i.e. The BU-65170X1 is interfaced the same as the BU-61580X1).
FIGURE 18. BU-65170/61580 INTERFACE TO A 1553 BUS
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TABLE 33. SIGNAL DESCRIPTIONS FOR BU-65170/61571, BU-61580/61585, BU-61586 (G, S or V PACKAGE) PROCESSOR/MEMORY INTERFACE AND CONTROL (15) SIGNAL NAME TRANSPARENT/ BUFFERED (1) STRBD (1) SELECT (1) MEM/REG (1) PIN DESCRIPTION
64 Used to select between the Transparent/ DMA mode (when strapped to logic 1) and the Buffered mode (when strapped to logic 0) for the host processor interface. 4 3 5 6 Strobe Data. Used with SELECT to initiate and control the data transfer cycle between the host processor and the BU65170/61580. Generally connected to a CPU address decoder output to select the BU-65170/61580 for a transfer to/from either RAM or register. May be tied to STRBD. Memory/Register. Generally connected to either a CPU address line or address decoder output. Selects between memory access (MEM/REG = 1 ) or register access (MEM/REG = 0 ). Read/Write. For host processor access, selects either reading or writing. In the 16-bit buffered mode, if polarity select is logic ), then RD/WR is low (logic 0 ) for read accesses and high (logic 1 ) for write accesses. If polarity select is logic 1 or the configuration of the interface is a mode other than 16-bit buffered mode, then RD/WR is high (logic 1 ) for read accesses and low (logic 0 ) for write accesses.
RD/WR (1)
IOEN (0)
67 Tri-state control for external address and data buffers. Generally not needed in the buffered mode. When low, external buffers should be to allow the host processor access to the BU-65170/61580's RAM and registers. 66 Handshake output to host processor. For a nonzero wait state read access, signals that data ia available to be read on D15 through D0. For a nonzero wait state write cycle, signals the completion of data transfer to a register or RAM location In the buffered zero wait state mode, active high output signal (following the rising edge of STRBD ) used to indicate the latching of address and data (write only) and that an internal transfer between the address/data latches and the RAM/registers is on-going. 65 Interrupt request output. If the LEVEL/PULSE interrupt bit (bit 3) of Configuration Register #2 is low, a negative pulse of approximately 500 ns in width is output on INT. If bit 3 is high, a low level interrupt request output will be asserted on INT. 31 Data Transfer Request or 16-bit/8-bit Transfer Mode Select. In transparent mode, active low output signal used to request access to the processor interface bus (address,data, and control buses). In buffered mode, input signal used to select between the 16-bit data transfer mode (16/8 = logic 1) and the 8 bit data transfer mode (16/8 = logic 0). 26 Data Transfer Grant or Most Significant Byte/Least Significant Byte. In transparent mode, active low input signal asserted, in response to the DTREQ output, to indicate that access to the processor buses has been granted to the BU65170/61580. In 8-bit buffered mode, input signal used to indicate which byte is being transferred (MSB or LSB). The POLARITY_SEL input controls the logic sense of MSB/LSB. (Note: only the 8-bit buffered mode uses MSB/LSB.) See description of POLARITY_SEL signal. N/C in 16-bit buffered mode. 32 Data Transfer Acknowledge or Polarity Select. In transparent mode, active low output signal used to indicate acceptance of the processor interface bus in response to a data transfer grant (DTGRT).In 16-bit buffered mode (TRANSPARENT/ BUFFERED = logic 0 and 16/8 = logic 1), input signal used to control the logic sense of the RD/WR signal. When POLARITY_SEL is logic 1, RD/WR must be asserted high (logic 1) for a read operation and low (logic 0) for a write operation. When POLARITY_SEL is logic 0, RD/WR must be asserted low (logic 0) for a read operation and high (logic 1) for a write operation.In 8-bit buffered mode (TRANSPARENT/BUFFERED = logic 0 and 16/8 = logic 0), input signal used to control the logic sense of the MSB/LSB signal. When POLARITY_SEL is logic 0, MSB/LSB must be asserted low (logic 0) to indicate the transfer of the least significant byte and high (logic 1) to indicate the transfer of the most significant byte. When POLARITY_SEL is logic 1, MSB/LSB must be asserted high (logic 1) to indicate the transfer of the least significant byte and low (logic 0) to indicate the transfer of the most significant byte. 28 Memory Enable Output. Asserted low during both host processor and 1553 protocol/memory management memory transfer cycles. Used as a memory chip select (CS) signal for external RAM in the transparent mode. 33 Memory Enable Input or Trigger Select. In transparent mode, MEMENA-IN is an active low Chip Select (CS) input to the 4K x 16 of internal shared RAM. When only using internal RAM, connect directly to MEMENA-OUT. In 8-bit buffered mode, the input signal (TRIGGER_SEL) indicates the order of byte pairs transfer to or from the BU-65170/61580 by the host processor. This signal has no operation (can be N/C) in the 16-bit buffered mode.In the 8-bit buffered mode, TRIGGER_SEL should be asserted high (logic 1) if the byte order for both read operations and write operations is MSB followed by LSB. TRIGGER_SEL should be asserted low (logic 0) if the byte order for both read operations and write operations is LSB followed by MSB. 29 Memory Output Enable or Address Latch. In transparent mode, MEMOE output will be used to enable data outputs for external RAM read cycles (normally connected to the OE signal on external RAM chips). In buffered mode, ADDR_LAT input will be used to configure the internal address latches in latched mode (when low) or transparent mode (when high). 30 Memory Write or Zero Wait State. In transparent mode, active low output signal (MEMWR ) will be asserted low during memory write transfers to strobe data into internal or external RAM (normally connected to the WR signal on external RAM chips). In buffered mode, input signal (ZERO_WAIT) will be used to select between the zero wait mode (ZERO_WAIT = logic 0) and the nonzero wait mode (ZERO_WAIT = logic 1).
READYD (0)
INT (O) DTREQ (O) /16/8 (I)
DTGRT (I) /MSB/LSB (I)
DTACK (O)/ POLARITY_SEL (I)
MEMENA-OUT (O)
MEMENA-IN (I) /TRIGGER_SEL (I)
MEMOE (O)/ ADDR_LAT (I)
MEMWR (O) /ZERO_WAIT (I)
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TABLE 33. SIGNAL DESCRIPTIONS FOR BU-65170/61571, BU-61580/61585, BU-61586 (G, S or V PACKAGE) (CONTINUED) MISCELLANEOUS (7) SIGNAL NAME CLOCK IN (I) MSTCLR (I) PIN 19 16MHz (or 12MHz) clock input. 7 Master Clear. Negative true Reset input, normally asserted low following power turn-on. Requires a minimum 100ns negative pulse to reset all internal logic to its "power turn-on" state. DESCRIPTION
INCMD (O)
45 In Command. In BC mode, asserted low throughout processing cycle for each message. In RT mode or Message Monitor mode, asserted low following receipt of Command Word and kept low until completion of current message sequence. In Word Monitor mode, goes low following MONITOR START command, kept low while monitor is on-line, goes high following RESET command. 27 Subsystem Flag or External Trigger input. In the Remote Terminal mode, asserting this input , will set the Subsystem Flag bit in the BU-65170/61580's RT Status Word. A low on the SSFLAG input overrides a logic "1" of the respective bit (bit 8) of Configuration Register #1. In the Bus Controller mode, an enabled external BC Start option (bit 7 of Configuration Register #1) and a low-to-high transition on this input will issue a BC Start command, starting execution of the current BC frame. In the Word Monitor mode, an enabled external trigger (bit 7 of Configuration Register #1) and a low-to-high transition on this input will issue a monitor trigger. 63 External Time Tag Clock input. Use may be designated by bits 7, 8, and 9 of Configuration Register #2. When used it increments the internal Time Tag Register/Counter. If not used, should be connected to +5V or ground. 70 Option for BU-65170/61580X6 and the BU-61585X6. Inhibits (disables) the respective (A/B) MIL-STD-1553 transmitter when asserted to logic "1." 36
SSFLAG (I)/ EXT_TRIG (I)
TAG_CLK (I) TX_INH_A (I) TX_INH_B (I)
POWER AND GROUND (8) SIGNAL NAME +5V LOGIC LOGIC GND -15(-12)VA +5VA GNDA -15(-12)VB +5VB GNDB PIN 54 Logic +5V Supply 18 Logic Ground 70 CH. A -15V(-12V) Supply* 68 CH. A +5V Supply 69 CH. A Transceiver Ground 36 CH. B -15V(-12V) Supply* 38 CH. B +5V Supply 37 CH. B Transceiver Ground DESCRIPTION
NOTE: * No Connects (N/Cs) for BU-65170/61580 and TX_INH input for BU-65170/61580X6.
RT ADDRESS (6) SIGNAL NAME RTAD4 (MSB) (I) RTAD3 (I) RTAD2 (I) RTAD1 (I) RTAD0 (LSB) (I) RTADP (I) PIN 43 Remote Terminal Address Inputs 42 41 40 39 44 Remote Terminal Address Parity. Must provide odd parity sum with RTAD4-RTAD0 in order for the RT to respond to nonbroadcast commands. DESCRIPTION
1553 ISOLATION TRANSFORMER INTERFACE (4) SIGNAL NAME TX/RX-A (I/O) TX/RX-A (I/O) TX/RX-B (I/O) TX/RX-B (I/O) PIN 1 2 34 35 DESCRIPTION Analog Transmit/Receive Input/Outputs. Connect directly to 1553 isolation transformers.
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TABLE 33. SIGNAL DESCRIPTIONS FOR BU-65170/61571, BU-61580/61585, BU-61586 (G, S or V PACKAGE) (CONTINUED) ADDRESS BUS (16) SIGNAL NAME PIN A15 (MSB) A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 8 DESCRIPTION
16-bit bidirectional address bus. In both the buffered and transparent modes, the host CPU accesses the BU-65170/61580 registers and 4K words of internal RAM by A11 through A0 (BU-61585 uses A13 through A0). The host CPU performs register 9 selection by A4 through A0.In the buffered mode, A15-A0 are inputs only. In the transparent mode, A15-A0 are inputs during 10 CPU accesses and drive outward (towards the CPU) when the 1553 protocol/memory management logic accesses up to 64K x 16 of external RAM. The address bus drives outward only in the transparent when the signal DTACK is low (indicating that 11 the 61580 has control of the processor interface bus) and IOEN is high (indicating that this is not a CPU access). Most of the 12 time, including immediately after power turn-on RESET, the A15-A0 outputs will be in their disabled (high impedance) state. 13 14 15 16 17 20 21 22 23 24 25
DATA BUS (16) SIGNAL NAME D15 (MSB) D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 PIN DESCRIPTION 62 16-bit bidirectional data bus. This bus interfaces the host processor to the internal registers and 4K words of RAM(12K of RAM for the BU-61585). In addition, in the transparent mode, this bus allows data transfers to take place between the 61 internal protocol/memory management logic and up to 64K x 16 of external RAM. Most of the time, the outputs for D15 60 through D0 are in their high impedance state. They drive outward in the buffered or transparent mode when the host CPU reads the internal RAM or registers. Or, in the transparent mode, when the protocol/memory management logic is 59 accessing (either reading or writing) internal RAM or writing to external RAM. 58 57 56 55 53 52 51 50 49 48 47 46
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TABLE 34. BU-65170/65171, BU-61580/61581/61585/61586 PIN LISTINGS (G, S or V PACKAGE) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 TX/RX-A TX/RX-A SELECT STRBD MEM/REG RD/WR MSTCLR A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 GND CLK A05 A04 A03 A02 A01 A00 DTGRT/MSB/LSB SSFLAG/EXT_TRIG MEMENA_OUT MEMOE/ADDR_LAT MEMWR/ZERO_WAIT DTREQ/16/8 DTACK/POLARITY_SEL MEMENA_IN/TRIGGER_SEL TX/RX-B TX/RX-B NAME PIN 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 NAME -VB (see note) GNDB +5VB RTAD0 RTAD1 RTAD2 RTAD3 RTAD4 RTADP INCMD D00 D01 D02 D03 D04 D05 D06 D07 +5V Logic D08 D09 D10 D11 D12 D13 D14 D15 TAG_CLK TRANSPARENT/BUFFERED INT READYD IOEN +5VA GNDA -VA (see note)
Notes: -15V for BU-65170/61580X1. -12V for BU-65170/61580X2. N/C for BU-65170/61580X3. For BU-65170/61580X6. pin 36 is TX_INH_B pin 70 is TX_INH_A
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0.215 (5.46) MAX FOR "D" PACKAGE 0.165 (4.19) MAX FOR "S" PACKAGE 0.180 0.010 TYP (4.57 0.25) 0.100 (2.54)
36 37 70 69
1.900 MAX (48.26)
0.400 (10.16)
0.600 (15.24)
34 35
BOTTOM VIEW
2
0.018 0.002 DIA TYP (0.46 0.05)
SIDE VIEW
0.100 (2.54) TYP 0.050 (1.27) TYP 1.700 (43.18) 1.900 (48.26) MAX
INDEX DENOTES PIN 1
1.000 MAX (25.4)
TOP VIEW
INDEX DENOTES PIN 1
NOTES: 1. DIMENSIONS ARE IN INCHES (MILLIMETERS). 2. PACKAGE MATERIAL: ALUMINA (AL2O3). 3. LEAD MATERIAL: KOVAR, PLATED BY 150 MINIMUM NICKEL, PLATED BY 50 MINIMUM GOLD.
FIGURE 19. BU-65170/65171/61580/61581/61585/61586S MECHANICAL OUTLINE
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1.900 MAX (48.26) 0.018 0.002 TYP (0.46 0.05) 0.215 (5.46) MAX For "F" Package 0.150 (3.81) MAX For "V" Package
70
36
INDEX DENOTES PIN 1
1.000 MAX (25.4)
1 0.400 MIN TYP (10.18) 0.050 TYP (1.27)
35
0.010 0.002 TYP (0.254 0.051) 34 EQ SP @ 0.050 = 1.700 (43.18) (1.27) TOL NONCUM 0.070 0.010 (1.78) PIN NUMBERS FOR REF ONLY
TOP VIEW
SIDE VIEW
NOTES: 1. DIMENSIONS ARE IN INCHES (MILLIMETERS). 2. PACKAGE MATERIAL: ALUMINA (AL2O3). 3. LEAD MATERIAL: KOVAR, PLATED BY 150 MINIMUM NICKEL, PLATED BY 50 MINIMUM GOLD.
FIGURE 20. BU-65170/65171/61580/61581/61585/61586V MECHANICAL OUTLINE
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PIN 1 DENOTED BY INDEX MARK 1
1.000 (MAX)
70
0.018 0.002
34 EQ. SP. @ 0.050 = 1.700 (TOL. NONCUM) 1.900 MAX 0.050 TYP
35
36
PIN NUMBERS ARE FOR REF. ONLY 0.150 MAX 0.190 0.010 0.065 (REF) 0.080 MIN
0.010 0.002
0.040 TYP 0.012 MAX 1.024 MAX 1.38 0.02 0.050 MIN
VIEW "A"
0.006 -0.004,+0.010 (0.152 +0.10,-0.254) VIEW "A"
FIGURE 21. BU-65170/65171/61580/61581/61585/61586G MECHANICAL OUTLINE
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ORDERING INFORMATION
BU-XXXXXXX-XXXX Supplemental Process Requirements: S = Pre-Cap Source Inspection L = Pull Test Q = Pull Test and Pre-Cap Inspection K = One Lot Date Code W = One Lot Date Code and PreCap Source Y = One Lot Date Code and 100% Pull Test Z = One Lot Date Code, PreCap Source and 100% Pull Test Blank = None of the Above Test Criteria: 0 = Standard Testing 2 = MIL-STD-1760 Amplitude Compliant - Applies to +5 Volt Transceiver Option Only Process Requirements: 0 = Standard DDC practices, no Burn-In (See following page.) 1 = MIL-PRF-38534 Compliant 2 = B* 3 = MIL-PRF-38534 Compliant with PIND Testing 4 = MIL-PRF-38534 Compliant with Solder Dip 5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip 6 = B* with PIND Testing 7 = B* with Solder Dip 8 = B* with PIND Testing and Solder Dip 9 = Standard DDC Processing with Solder Dip, no Burn-In (See following page.) Temperature Range/Data Requirements: 1 = -55C to +125C 2 = -40C to +85C 3 = 0C to +70C 4 = -55C to +125C with Variables Test Data 5 = -40C to +85C with Variables Test Data 8 = 0C to +70C with Variables Test Data Voltage/Transceiver Option: 0 = Transceiverless 1 = +5 Volts and -15 Volts (1760 Compliant - Standard Configuration) 2 = +5 Volts and -12 Volts 3 = +5 Volts, rise/fall times=100 to 300 ns (-1553B)(See Test Criteria - 1760 Compliant with option -XX2) 5 = +5/+15/-15V Sinusoidal (McAir) 6 = +5 Volts only with TX Inhibit inputs brought out on negative supply pins Package Type: G = "Gull Wing" (Formed Lead) J = J Lead (Solder DIP not available ) P = PGA S = Small DIP V = Very Small Flat Pack Product Type: 65170 = 70-pin RT 65171 = 70-pin RT with Latchable RT Address Option 61580 = 70-pin BC/RT/MT 61581 = 70-pin BC/RT/MT with Latchable RT address Option 61585 = 70-pin BC/RT/MT 8K x 17 with RAM 61586 = 70-pin BC/RT/MT 8K x 17 with RAM and RT Address Option Note: The ACE series is also available to DESC drawing number 5962-93065. *Standard DDC Processing with burn-in and full temperature test, see table on following page.
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STANDARD DDC PROCESSING MIL-STD-883 TEST METHOD(S) INSPECTION SEAL TEMPERATURE CYCLE CONSTANT ACCELERATION BURN-IN 2009, 2010, 2017, and 2032 1014 1010 2001 1015, Table 1 CONDITION(S) -- A and C C A --
The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice.
105 Wilbur Place, Bohemia, New York, U.S.A. 11716-2482 For Technical Support - 1-800-DDC-5757 ext. 7234 Headquarters, N.Y., U.S.A. - Tel: (631) 567-5600, Fax: (631) 567-7358 Southeast, U.S.A. - Tel: (703) 450-7900, Fax: (703) 450-6610 West Coast, U.S.A. - Tel: (714) 895-9777, Fax: (714) 895-4988 United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 Ireland - Tel: +353-21-341065, Fax: +353-21-341568 France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425 Germany - Tel: +49-(0)8141-349-087, Fax: +49-(0)8141-349-089 Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide Web - http://www.ddc-web.com
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DATA DEVICE CORPORATION REGISTERED TO ISO 9001 FILE NO. A5976
PRINTED IN THE U.S.A.
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RM
U
REG
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